发明授权
US5976945A Method for fabricating a DRAM cell structure on an SOI wafer
incorporating a two dimensional trench capacitor
失效
在包含二维沟槽电容器的SOI晶片上制造DRAM单元结构的方法
- 专利标题： Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor
- 专利标题（中）： 在包含二维沟槽电容器的SOI晶片上制造DRAM单元结构的方法
-
申请号： US974452申请日： 1997-11-20
-
公开(公告)号： US5976945A公开(公告)日： 1999-11-02
- 发明人: Min-Hwa Chi , Chih-Yuan Lu
- 申请人： Min-Hwa Chi , Chih-Yuan Lu
- 申请人地址： TWX Hsin-Chu
- 专利权人： Vanguard International Semiconductor Corporation
- 当前专利权人： Vanguard International Semiconductor Corporation
- 当前专利权人地址： TWX Hsin-Chu
- 主分类号： H01L21/8242
- IPC分类号： H01L21/8242 ; H01L21/84 ; H01L27/108 ; H01L27/12 ; H01L21/20
摘要：
A method for fabricating a DRAM cell, on a SOI layer, is described, featuring the incorporation of a two dimensional, trench capacitor structure, for increased DRAM cell signal, and the use of a polysilicon storage node structure to connect the SOI layer to the semiconductor substrate, to eliminate a floating body effect. A two dimensional trench is created by initially forming a vertical trench, through the SOI layer, through the underlying insulator layer, and into the semiconductor substrate. An isotropic etch is than performed to laterally remove a specific amount of insulator layer, exposed in the vertical trench, creating the lateral component of the two dimensional trench. A deposited polysilicon layer, coating the sides of the two dimensional trench, is used as the storage node structure, for the two dimensional, trench capacitor structure, while also connecting the SOI layer to the semiconductor substrate.
公开/授权文献
- US5280882A Electromagnetic valve 公开/授权日：1994-01-25
信息查询
IPC分类:
