A method of forming edge metal lines to interconnect features in a semiconductor device. One embodiment comprises the steps of: patterning a first insulating layer to form a first feature having a first sidewall; depositing a metal layer over the first feature; and etching the metal layer so that a first edge metal line is formed adjacent to the first sidewall. The edge metal line may be substantially anisotropically etched to form the edge metal line. The edge metal line may comprise a plurality of metal layers. The edge metal line may also interconnect features in a semiconductor device (e.g., contacts). The method may further comprise the step of forming a protective coating over a portion of the metal layer such that the etching step may form a metal interconnect line and the edge metal line from the same metal layer. The metal interconnect line may comprise a bus that may have more current carrying capacity than the edge metal line.