公开(公告)号：US06185126B2

公开(公告)日：2001-02-06

申请号：US08805890

申请日：1997-03-03

Applicant: T. J. Rodgers ,  W. Alfred Graf, III

Inventor： T. J. Rodgers ,  W. Alfred Graf, III

IPC: G11C1100

CPC classification number: G11C5/06 ,  G11C7/1006 ,  G11C7/20 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17772 ,  H03K19/1778

Abstract: A programmable logic device includes a node and a RAM cell configured to power-up in a preferred state so as to provide a predetermined logic signal to the node upon power-up. The node may comprise an interconnection element, for example a transistor. Associated with the interconnection element may be two signal lines within the programmable logic device, for example, as part of a programmable interconnect matrix. The interconnection element and the two signal lines are associated such that when the interconnection element is in a first state the two signal lines are electrically coupled and when the interconnection element is in a second state the two signal lines are not electrically coupled. The predetermined logic signal from the RAM cell selects one of the first and second states. The RAM cell may include two PMOS transistors, each having an associated threshold voltage, wherein the threshold voltage of one of the PMOS transistors is lower than the threshold voltage of the other PMOS transistor. The RAM cell may be included in a look-up table such that the node is an output of the look-up table. Alternatively, the programmable logic device may further include a multiplexer wherein the RAM cell is coupled to the data path input of the multiplexer through the node. In other embodiments, the RAM cell may act as a select cell for the multiplexer.

Abstract translation: 可编程逻辑器件包括被配置成在优选状态下上电的节点和RAM单元，以便在上电时向节点提供预定的逻辑信号。 节点可以包括互连元件，例如晶体管。 与互连元件相关联的可以是可编程逻辑器件内的两条信号线，例如，作为可编程互连矩阵的一部分。 互连元件和两个信号线相关联，使得当互连元件处于第一状态时，两个信号线电耦合，并且当互连元件处于第二状态时，两个信号线不电耦合。 来自RAM单元的预定逻辑信号选择第一和第二状态之一。 RAM单元可以包括两个PMOS晶体管，每个具有相关联的阈值电压，其中一个PMOS晶体管的阈值电压低于另一个PMOS晶体管的阈值电压。 RAM单元可以被包括在查找表中，使得节点是查找表的输出。 或者，可编程逻辑器件还可以包括多路复用器，其中RAM单元通过节点耦合到多路复用器的数据路径输入。 在其他实施例中，RAM单元可以用作多路复用器的选择单元。

公开(公告)号：US5835401A

公开(公告)日：1998-11-10

申请号：US760823

申请日：1996-12-05

Applicant: Gary W. Green ,  John Q. Torode ,  T. J. Rodgers ,  Shailesh Shah

Inventor： Gary W. Green ,  John Q. Torode ,  T. J. Rodgers ,  Shailesh Shah

IPC: G11C11/406 ,  G11C11/24

CPC classification number: G11C11/406

Abstract: A method and circuit for hiding a refresh of DRAM cells in a memory device. One embodiment of the circuit includes a selection circuit configured to select a first row of DRAM cells in the memory circuit in response to an active control signal. As a result, data may be read from or written to at least one of the DRAM cells in the first row. The selection circuit is also configured to couple a refresh address to a second row of DRAM cells in the memory circuit in response to an inactive state control signal. The second row of cells is refreshed when the selection circuit accesses the second row. For one embodiment, the DRAM cells are four transistor DRAM cells.

Abstract translation: 一种用于将DRAM单元的刷新隐藏在存储器件中的方法和电路。 电路的一个实施例包括选择电路，其被配置为响应于主动控制信号选择存储器电路中的第一行DRAM单元。 结果，数据可以从第一行的DRAM单元中的至少一个读取或写入。 选择电路还被配置为响应于非活动状态控制信号将刷新地址耦合到存储器电路中的第二行DRAM单元。 当选择电路访问第二行时，第二行单元格被刷新。 对于一个实施例，DRAM单元是四个晶体管DRAM单元。

公开(公告)号：US5977638A

公开(公告)日：1999-11-02

申请号：US754521

申请日：1996-11-21

Applicant: T. J. Rodgers ,  Sam Geha ,  Chris Petti ,  Ting-Pwu Yen

Inventor： T. J. Rodgers ,  Sam Geha ,  Chris Petti ,  Ting-Pwu Yen

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/528 ,  H01L27/11 ,  H01L23/48 ,  H01L21/44

CPC classification number: H01L27/11 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/528 ,  H01L27/1104 ,  H01L2924/0002

Abstract: A method of forming edge metal lines to interconnect features in a semiconductor device. One embodiment comprises the steps of: patterning a first insulating layer to form a first feature having a first sidewall; depositing a metal layer over the first feature; and etching the metal layer so that a first edge metal line is formed adjacent to the first sidewall. The edge metal line may be substantially anisotropically etched to form the edge metal line. The edge metal line may comprise a plurality of metal layers. The edge metal line may also interconnect features in a semiconductor device (e.g., contacts). The method may further comprise the step of forming a protective coating over a portion of the metal layer such that the etching step may form a metal interconnect line and the edge metal line from the same metal layer. The metal interconnect line may comprise a bus that may have more current carrying capacity than the edge metal line.

Abstract translation: 一种形成边缘金属线以在半导体器件中互连特征的方法。 一个实施例包括以下步骤：图案化第一绝缘层以形成具有第一侧壁的第一特征; 在第一特征上沉积金属层; 并且蚀刻所述金属层，使得与所述第一侧壁相邻地形成第一边缘金属线。 边缘金属线可以被基本上各向异性地蚀刻以形成边缘金属线。 边缘金属线可以包括多个金属层。 边缘金属线还可以互连半导体器件（例如，触点）中的特征。 该方法还可以包括在金属层的一部分上形成保护涂层的步骤，使得蚀刻步骤可以从同一金属层形成金属互连线和边缘金属线。 金属互连线可以包括可以具有比边缘金属线更多的载流能力的总线。