A fault protection arrangement for protecting power conversion circuits, for example switch mode power supplies and the like, from overcurrent and short circuit faults. The fault protection arrangement includes multiple fault protection features, for example soft-start delay, fault delay and automatic reset, with the timing of each of these three features capable of being set independently of the other two while minimizing integrated circuit (IC) pin count and also minimizing the number of external components required for programming the timing of these features. The fault protection circuit may be used to advantage with any power conversion regulator topology.