A methodology and implementing system 101 are provided in which a PCI bus is enhanced to operate at a plurality of data transfer speeds, including for example, 133 MHz in order to accommodate subsystem boards operating at higher frequencies, while at the same time allowing normal 66 MHz PCI clocking for devices designed to operate at the lower 66 MHz standard PCI speed. Master strobe MSTB 303, 403 and target strobe TSTB signals 309, 411 are generated in a handshaking methodology to determine if a master data transaction requesting device and a target data transaction device are designed to operate at the higher data transfer frequency. Higher frequency capable devices or boards are run at the increased frequency when both the requesting master and the selected target devices request the higher transfer rate, and standard devices or boards are run at the lower standard PCI frequency, while both master and target devices are coupled to and run from the same multi-speed PCI bus 125.