发明授权
- 专利标题: Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit
- 专利标题(中): 半导体电路的互连迹线之间的低介电常数材料的最大化
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申请号: US805607申请日: 1997-02-25
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公开(公告)号: US5990009A公开(公告)日: 1999-11-23
- 发明人: Cheng-Chen Hsueh , Shih-Ked Lee , Chuen-Der Lien
- 申请人: Cheng-Chen Hsueh , Shih-Ked Lee , Chuen-Der Lien
- 申请人地址: CA Santa Clara
- 专利权人: Integrated Device Technology, Inc.
- 当前专利权人: Integrated Device Technology, Inc.
- 当前专利权人地址: CA Santa Clara
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L21/302
摘要:
A structure and method of maximizing the volume of low dielectric constant material between adjacent traces of a conductive interconnect structure. A semiconductor structure includes a semiconductor substrate, a first insulating layer located over the semiconductor substrate, a conductive interconnect layer having a plurality of conductive traces located over the first insulating layer, and a patterned insulating layer located over the patterned interconnect layer. One or more trenches are formed in the upper surface of the first insulating layer. These trenches, which do not extend completely through the first insulating layer, are located between adjacent traces of the interconnect layer. A dielectric material having a low dielectric constant is located in these trenches, and between adjacent traces of the patterned interconnect layer. The trenches advantageously maximize the volume of low dielectric constant material which is located between the traces.
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