公开(公告)号：US07877657B1

公开(公告)日：2011-01-25

申请号：US11960618

申请日：2007-12-19

申请人： Michael Miller ,  Chuen-Der Lien

发明人： Michael Miller ,  Chuen-Der Lien

IPC分类号： G01R31/3187 ,  G01R31/40

CPC分类号： G01R31/3016 ,  G01R31/318519

摘要： A method and apparatus are disclosed for predicting the failure of a functional element of an integrated circuit during operation. The method includes determining whether the functional element of the integrated circuit device is in an idle cycle, performing a stress test of the functional element while the functional element is in the idle cycle, and indicating that the functional element, if it fails the stress test, is a potential future failing element. The stress test can include simultaneously providing a margining test voltage and a stress clock signal to the functional element. The stress test is performed in the background, during continuous operation of the integrated circuit device, such that normal operation of the integrated circuit device is not interrupted. Thereby, the method and apparatus of the present invention allows for failure prediction in a device before it happens, allowing for planned outages or workarounds and avoiding system downtime for unplanned repairs.

摘要翻译： 公开了一种用于在操作期间预测集成电路的功能元件的故障的方法和装置。 该方法包括：确定集成电路器件的功能元件是否处于空闲周期，在功能元件处于空闲周期内执行功能元件的应力测试，并且指示功能元件（如果其失效） ，是一个未来潜在的潜在因素。 应力测试可以包括同时向功能元件提供裕度测试电压和应力时钟信号。 在集成电路装置的连续运行期间，在背景中执行应力测试，使得集成电路装置的正常操作不被中断。 因此，本发明的方法和装置允许在装置发生之前对装置进行故障预测，从而允许计划中断或解决方案，并避免计划外维修的系统停机时间。

公开(公告)号：US07414460B1

公开(公告)日：2008-08-19

申请号：US11395061

申请日：2006-03-31

申请人： Chuen-Der Lien ,  Chau-Chin Wu ,  Tzong-Kwang Yeh

发明人： Chuen-Der Lien ,  Chau-Chin Wu ,  Tzong-Kwang Yeh

IPC分类号： G05F3/02

CPC分类号： H02M3/07

摘要： A charge recycling integrated circuit and a method for integrated circuit charge recycling. In one aspect, a charge storage collector is interposed between a high voltage supply or a low voltage supply and a function block of the integrated circuit. The charge collector is operable to selectively store a charge dissipated in the function block when the logic circuitry of the function block switches between a high voltage value and a low voltage value. The dissipated charge resulting from the switching in the logic circuitry of the function block is selectively stored to the charge collector and the charge collector selectively returns the charge stored on the charge collector to the high voltage supply, the low voltage supply or to another node in the integrated circuit as appropriate.

摘要翻译： 电荷回收集成电路和集成电路充电回收方法。 在一个方面，电荷存储收集器介于高压电源或低压电源和集成电路的功能块之间。 当功能块的逻辑电路在高电压值和低电压值之间切换时，电荷收集器可操作以选择性地存储消耗在功能块中的电荷。 由功能块的逻辑电路中的开关导致的耗散电荷被选择性地存储到电荷收集器中，并且电荷收集器选择性地将存储在电荷收集器上的电荷返回到高电压源，低电压电源或另一个节点 集成电路适当。

公开(公告)号：US07248492B1

公开(公告)日：2007-07-24

申请号：US11393985

申请日：2006-03-30

申请人： Chuen-Der Lien ,  Chau-Chin Wu

发明人： Chuen-Der Lien ,  Chau-Chin Wu

IPC分类号： G11C15/00 ,  G11C7/00

CPC分类号： G11C15/04 ,  G11C7/02

摘要： A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.

公开(公告)号：US07050317B1

公开(公告)日：2006-05-23

申请号：US10927453

申请日：2004-08-26

申请人： Chuen-Der Lien ,  Kee Park ,  Scott Yu-Fan Chu

发明人： Chuen-Der Lien ,  Kee Park ,  Scott Yu-Fan Chu

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： Content addressable memory (CAM) devices include at least one CAM array having a plurality of columns of ternary CAM cells therein. A bit/data line driver circuit, which receives search words and write words, is electrically coupled to the CAM array. The bit/data line driver circuit is configured to save power by logically combining incoming search words with a global mask that designates locations of active ones of the plurality of columns having exclusively locally masked CAM cells at valid entries therein. The bit/data line driver circuit includes a global mask generator configured to receive write words to be added to the CAM array during respective write operations.

摘要翻译： 内容可寻址存储器（CAM）设备包括其中具有多列三元CAM单元的至少一个CAM阵列。 接收搜索字和写入字的位/数据线驱动电路电耦合到CAM阵列。 位/数据线驱动器电路被配置为通过逻辑地组合传入的搜索词与通过在其中的有效条目中指定了具有本地掩蔽的CAM单元的多个列中的活动的列的位置的全局掩码来节省功率。 位/数据线驱动器电路包括全局掩模生成器，其被配置为在各个写入操作期间接收要添加到CAM阵列的写入字。

公开(公告)号：US20060028860A1

公开(公告)日：2006-02-09

申请号：US10997708

申请日：2004-11-23

申请人： Chuen-Der Lien ,  Tzong-Kwang Yeh

发明人： Chuen-Der Lien ,  Tzong-Kwang Yeh

IPC分类号： G11C11/00

CPC分类号： G11C8/16 ,  G11C5/063 ,  G11C7/02 ,  G11C7/12 ,  G11C11/419

摘要： Capacitive coupling correction circuits are coupled between adjacent parallel dynamic (pre-charged) or static conductors. The capacitive coupling correction circuits effectively isolate a low voltage applied to a first conductor from a high pre-charged voltage stored on an adjacent second conductor (or vice versa). The adjacent parallel conductors can be bit lines of a memory cell. Each capacitive coupling correction circuit can include an inverter having an input terminal coupled to the first conductor, and an output terminal coupled to a first plate of a capacitor. A second plate of the capacitor is coupled to the second conductor. The capacitance of the capacitor is selected to be identical to a parasitic capacitance between the first and second conductors. As a result, there is a zero net voltage effect between the first and second conductors. The capacitive coupling correction circuits may be distributed along the length of the first and second conductors.

摘要翻译： 电容耦合校正电路耦合在相邻的并联动态（预充电）或静态导体之间。 电容耦合校正电路有效地将施加到第一导体的低电压与存储在相邻的第二导体上的高预充电电压隔离（反之亦然）。 相邻的平行导体可以是存储单元的位线。 每个电容耦合校正电路可以包括具有耦合到第一导体的输入端的反相器和耦合到电容器的第一板的输出端。 电容器的第二板耦合到第二导体。 电容器的电容被选择为与第一和第二导体之间的寄生电容相同。 结果，在第一和第二导体之间存在零净电压效应。 电容耦合校正电路可以沿着第一和第二导体的长度分布。

公开(公告)号：US06870749B1

公开(公告)日：2005-03-22

申请号：US10619635

申请日：2003-07-15

申请人： Kee Park ,  Chuen-Der Lien

发明人： Kee Park ,  Chuen-Der Lien

IPC分类号： G06F11/10 ,  G11C7/00 ,  G11C15/00 ,  G11C29/00 ,  G11C29/42

CPC分类号： G11C29/70 ,  G06F11/1064 ,  G11C15/00 ,  G11C29/42

摘要： Content addressable memory (CAM) devices include dual-function check bit cells that can operate as check bit cells to support error detection and correction (EDC) operations or as redundant CAM cells that support column redundancy. Dedicated check bit cells are also provided that have a reduced susceptibility to soft errors relative to adjacent CAM cells. The dedicated check bit cells may also be provided within a global mask cell sub-array to support correction of soft errors within global masks.

摘要翻译： 内容可寻址存储器（CAM）设备包括双功能校验位单元，其可以用作校验位单元来支持错误检测和校正（EDC）操作，或者作为支持列冗余的冗余CAM单元。 还提供专用校验位单元，其相对于相邻的CAM单元具有降低的对软误差的敏感性。 专用校验位单元也可以被提供在全局掩模单元子阵列内以支持全局掩模内的软错误的校正。

公开(公告)号：US06754093B2

公开(公告)日：2004-06-22

申请号：US10165506

申请日：2002-06-06

申请人： Chuen-Der Lien

发明人： Chuen-Der Lien

IPC分类号： G11C1500

CPC分类号： G11C15/043 ,  G11C5/005 ,  G11C15/04

摘要： A CMOS CAM circuit an array of CAMs formed on a p-type substrate. Each CAM cell includes a logic portion and an SRAM cell, both having at least one n-channel transistor formed in a p-type well on the p-type substrate. An n-type doped layer is formed between the p-type well region and the p-substrate that attracts electron-hole pairs formed by alpha particles, thereby preventing soft errors. Alternatively, the logic portions and SRAM cells have p-channel transistors formed in n-type wells on an n-type substrate, and a p-type doped layer is formed between the n-type well region and the n-substrate.

摘要翻译： CMOS CAM电路形成在p型衬底上的CAM阵列。 每个CAM单元包括逻辑部分和SRAM单元，它们都具有形成在p型衬底上的p型阱中的至少一个n沟道晶体管。 在p型阱区域和p型衬底之间形成n型掺杂层，其吸引由α粒子形成的电子 - 空穴对，从而防止软错误。 或者，逻辑部分和SRAM单元具有形成在n型衬底上的n型阱中的p沟道晶体管，在n型阱区和n衬底之间形成p型掺杂层。

公开(公告)号：US06724601B2

公开(公告)日：2004-04-20

申请号：US09811114

申请日：2001-03-16

申请人： Chuen-Der Lien ,  Chau-Chin Wu ,  Ta-Ke Tien

发明人： Chuen-Der Lien ,  Chau-Chin Wu ,  Ta-Ke Tien

IPC分类号： H02H900

CPC分类号： H01L27/0251

摘要： An integrated circuit having an electrostatic discharge (ESD) protection circuit, a core protection circuit, a sensitive core circuit and peripheral circuitry is provided. The ESD protection circuit is coupled between the VDD voltage supply terminal and the VSS voltage supply terminal, and is capable of providing protection to the peripheral circuitry. The ESD protection circuitry requires help from core protection circuit to protect the sensitive core circuit. The core protection circuit and the sensitive core circuit are coupled in series between the VDD and VSS voltage supply terminals, with the core protection circuit coupled to the VDD voltage supply terminal. The sensitive core circuit has a VCC voltage supply terminal coupled to receive a VCC supply voltage from the core protection circuit. The core protection circuit is configured to cause the VCC supply voltage to rise slowly with respect to a rising voltage on the VDD voltage supply terminal during power-on of the integrated circuit. The core protection circuit is further configured to disconnect the VCC voltage supply terminal from the VDD voltage supply when a voltage on the VDD voltage supply terminal exceeds the nominal VDD supply voltage by a predetermined amount.

摘要翻译： 提供具有静电放电（ESD）保护电路，核心保护电路，敏感核心电路和外围电路的集成电路。 ESD保护电路耦合在VDD电压端子和VSS电压端子之间，能够为外围电路提供保护。 ESD保护电路需要核心保护电路的帮助来保护敏感的核心电路。 核心保护电路和敏感核心电路串联在VDD和VSS电压端子之间，核心保护电路耦合到VDD电源端。 敏感核心电路具有VCC电压供应端，耦合以从核心保护电路接收VCC电源电压。 核心保护电路被配置为使得在电源上的VCC电源电压相对于VDD电压端上升的电压缓慢上升。 核心保护电路还被配置为当VDD电压端子上的电压超过标称VDD电源电压预定量时，将VCC电压源端子与VDD电压源断开。

公开(公告)号：US06661687B1

公开(公告)日：2003-12-09

申请号：US10350991

申请日：2003-01-23

申请人： Chuen-Der Lien ,  Chau-Chin Wu

发明人： Chuen-Der Lien ,  Chau-Chin Wu

IPC分类号： G11C1500

CPC分类号： G11C15/00 ,  G11C14/00 ,  G11C15/04 ,  G11C15/043

摘要： A CAM circuit utilizes a relatively high operating voltage to control the memory portion of each CAM cell, and a relatively low operating voltage to control at least some of the logic portions of each CAM circuit. The CAM cell memory portion includes a memory (e.g., SRAM) cell controlled by a word line to store data values transmitted on complementary bit lines. The CAM cell logic portion includes a comparator that compares the stored data values with an applied data value transmitted on complementary data lines, and discharges a match line when the stored data value differs from the applied data value. The memory cell is driven using the relatively high memory operating voltage (e.g., 2.5 Volts) such that the stored charge resists soft errors. The complementary data lines and match line used to operate the comparator are driven using the relatively low logic operating voltage (e.g., 1.2 Volts) to conserve power.

摘要翻译： CAM电路利用相对高的工作电压来控制每个CAM单元的存储器部分，以及相对低的工作电压来控制每个CAM电路的至少一些逻辑部分。 CAM单元存储器部分包括由字线控制的存储器（例如，SRAM）单元，以存储在互补位线上传输的数据值。 CAM单元逻辑部分包括比较器，用于比较存储的数据值和互补数据线上传输的应用数据值，并且当存储的数据值与应用的数据值不同时，对其进行放电。 使用相对高的存储器工作电压（例如，2.5伏特）来驱动存储器单元，使得存储的电荷抵抗软错误。 用于操作比较器的补充数据线和匹配线使用相对较低的逻辑工作电压（例如，1.2伏特）来驱动以节省功率。

公开(公告)号：US06657878B2

公开(公告)日：2003-12-02

申请号：US10084842

申请日：2002-02-27

申请人： Chuen-Der Lien ,  Chau-Chin Wu

发明人： Chuen-Der Lien ,  Chau-Chin Wu

IPC分类号： G11C1500

CPC分类号： G11C15/04 ,  G11C15/00 ,  G11C29/816

摘要： Content addressable memory (CAM) devices provide improved reliability by inhibiting disabled CAM cells within defective (or unused redundant columns) from contributing to either sustained or intermittent look-up errors when the CAM device is operated in an intended application. The improved reliability may be achieved in volatile CAM devices by configuring (e.g., programming) each column driver that is associated with a CAM array having a defective column therein to preserve intentionally written data and/or mask values of the disabled CAM cells across repeated power reset events.

摘要翻译： 内容可寻址存储器（CAM）器件通过禁止在缺陷（或未使用的冗余列）中的禁用的CAM单元在CAM设备在预期应用中操作时造成持续或间歇查找错误而提供改进的可靠性。 通过配置（例如，编程）与其中具有缺陷列的CAM阵列相关联的每个列驱动器，可以在易失性CAM设备中实现改进的可靠性，以保留有效地写入的数据和/或禁用的CAM单元的重复功率的屏蔽值 复位事件。