发明授权
US5994178A Method of fabricating CMOS transistors with a planar shallow trench
isolation
失效
制造具有平面浅沟槽隔离的CMOS晶体管的方法
- 专利标题： Method of fabricating CMOS transistors with a planar shallow trench isolation
- 专利标题（中）： 制造具有平面浅沟槽隔离的CMOS晶体管的方法
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申请号： US001978申请日： 1997-12-31
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公开(公告)号： US5994178A公开(公告)日： 1999-11-30
- 发明人: Shye-Lin Wu
- 申请人： Shye-Lin Wu
- 申请人地址： TWX Hsinchu
- 专利权人： Texas Instruments - Acer Incorporated
- 当前专利权人： Texas Instruments - Acer Incorporated
- 当前专利权人地址： TWX Hsinchu
- 主分类号： H01L21/762
- IPC分类号： H01L21/762 ; H01L21/8238
摘要：
The present invention discloses a method of forming CMOS transistors with planar shallow trench isolations. Before a twin well being formed, a pad oxide film and a nitride film are sequentially deposited on a silicon substrate. When a photoresist film is patterned to define active regions, the silicon substrate is recessed by using the patterned photoresist film as a mask. A liquid-phase-deposition oxide (LPD) film is then grown on the recess structure for shallow trench isolations. Next, a high temperature annealing procedure is performed to densify the LPD oxide film. Finally, when the pad oxide and the nitride films are removed, processes for fabricating CMOS transistors can be continued on the silicon substrate.
公开/授权文献
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