公开(公告)号：US07368371B2

公开(公告)日：2008-05-06

申请号：US11453801

申请日：2006-06-16

申请人： Shye-Lin Wu

发明人： Shye-Lin Wu

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L21/8213 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n− silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried out to dope the silicon layer. Afterward the doped silicon layer is patterned to define an active region. A thermal oxidation is then followed to form a thick oxide layer by oxidizing the silicon layer and form guard rings by using the doped silicon layer as a diffused source. The thin oxide layer on the drift layer is then removed by dilute HF dip or by BOE (buffer oxide etching) solution dip. Thereafter, a top metal layer is deposited and patterned to define as anode. After a backside layer removal, a metal layer served as cathode is formed.

摘要翻译： 公开了一种形成碳化硅肖特基二极管的方法。 这些过程只需要两个照相掩模。 工艺如下：首先，提供具有碳化硅漂移层的n + - 碳化硅衬底。 然后在漂移层上形成硅层。 进行离子注入以掺杂硅层。 之后，将掺杂硅层图案化以限定有源区。 然后通过氧化硅层并通过使用掺杂硅层作为扩散源形成保护环，随后进行热氧化以形成厚氧化物层。 然后通过稀释HF浸渍或通过BOE（缓冲氧化物蚀刻）溶液浸渍除去漂移层上的薄氧化物层。 此后，沉积顶层金属层并图案化以将其定义为阳极。 在去除背面层之后，形成用作阴极的金属层。

公开(公告)号：US20070293028A1

公开(公告)日：2007-12-20

申请号：US11453799

申请日：2006-06-16

申请人： Shye-Lin Wu

发明人： Shye-Lin Wu

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L21/26513 ,  H01L21/2658 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/872

摘要： A method of forming a power Schottky rectifier device is disclosed. The Schottky rectifier device including LOCOS structure and two p doped layers formed thereunder to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n− drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n− drift layer; a pair of field oxide regions and termination field oxide region formed into the n− drift layer and each spaced from each other by the mesas. A stack of metal layers formed of Ti/Ni/Ag are formed atop the front surface. A RTP (rapid thermal process) is then followed to form a Schottky barrier diode. Alternatively, the stack metal layers are formed of Ti/TiN/Al. Yet, the Al is formed after RTP. Subsequently, the top metal layer is patterned to form an anode electrode.

摘要翻译： 公开了一种形成功率肖特基整流器件的方法。 肖特基整流器包括LOCOS结构和两个p掺杂层形成在其下面，以避免击穿电压过早。 肖特基整流器件包括：形成在n +衬底上的n-漂移层; 形成在与n漂移层相对的n +衬底的表面上的阴极金属层; 一对场氧化物区域和终止场氧化物区域，形成在n漂移层中，并且每个通过台面彼此间隔开。 由Ti / Ni / Ag形成的一叠金属层形成在前表面的顶部。 然后按照RTP（快速热处理）形成肖特基势垒二极管。 或者，堆叠金属层由Ti / TiN / Al形成。 然而，Al是在RTP之后形成的。 随后，对顶部金属层进行图案化以形成阳极电极。

公开(公告)号：US20070293001A1

公开(公告)日：2007-12-20

申请号：US11453801

申请日：2006-06-16

申请人： Shye-Lin Wu

发明人： Shye-Lin Wu

IPC分类号： H01L21/8234

CPC分类号： H01L21/8213 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n− silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried out to dope the silicon layer. Afterward the doped silicon layer is patterned to define an active region. A thermal oxidation is then followed to form a thick oxide layer by oxidizing the silicon layer and form guard rings by using the doped silicon layer as a diffused source. The thin oxide layer on the drift layer is then removed by dilute HF dip or by BOE (buffer oxide etching) solution dip. Thereafter, a top metal layer is deposited and patterned to define as anode. After a backside layer removal, a metal layer served as cathode is formed.

摘要翻译： 公开了一种形成碳化硅肖特基二极管的方法。 这些过程只需要两个照相掩模。 工艺如下：首先，提供具有碳化硅漂移层的n + - 碳化硅衬底。 然后在漂移层上形成硅层。 进行离子注入以掺杂硅层。 之后，将掺杂硅层图案化以限定有源区。 然后通过氧化硅层并通过使用掺杂硅层作为扩散源形成保护环，随后进行热氧化以形成厚氧化物层。 然后通过稀释HF浸渍或通过BOE（缓冲氧化物蚀刻）溶液浸渍除去漂移层上的薄氧化物层。 此后，沉积顶层金属层并图案化以将其定义为阳极。 在去除背面层之后，形成用作阴极的金属层。

公开(公告)号：US06342422B1

公开(公告)日：2002-01-29

申请号：US09439433

申请日：1999-11-15

申请人： Shye-Lin Wu

发明人： Shye-Lin Wu

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/28035 ,  H01L21/28247 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

摘要： A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. A first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, the first silicon layer, and the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and the first dielectric layer is removed. A second silicon layer is formed on the semiconductor substrate and on the first silicon layer. Another doping step is performed to dope the second silicon layer. A series of process is then performed to form a metal silicide layer on the second silicon layer and also to diffuse and activate the doped dopants.

摘要翻译： 在半导体衬底上形成栅极绝缘体层，然后在栅极绝缘体层上形成第一硅层。 第一介电层形成在第一硅层之上。 通过去除栅极绝缘体层，第一硅层和第一介电层的一部分来限定栅极区域。 执行使用低能量注入或等离子体浸没的掺杂步骤以掺杂衬底，以在由栅极区域未覆盖的区域下在衬底中形成扩展的源极/漏极结。 在栅极区域的侧壁上形成未掺杂的间隔结构，并且去除第一介电层。 在半导体衬底上和第一硅层上形成第二硅层。 执行另一掺杂步骤以掺杂第二硅层。 然后执行一系列处理以在第二硅层上形成金属硅化物层，并且还扩散和激活掺杂的掺杂剂。

公开(公告)号：US06255167B1

公开(公告)日：2001-07-03

申请号：US09325810

申请日：1999-06-04

申请人： Shye-Lin Wu

发明人： Shye-Lin Wu

IPC分类号： H01L21336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of fabricating buried bit line flash EEROM cells with shallow trench floating gates for suppressing the short channel effect is disclosed. The method includes the following steps. First, a first polysilicon layer with conductive impurities and a nitride capping layer are sequentially formed on a silicon substrate. The nitride cap layer serves as an anti-reflection coating (ARC) layer for improving the resolution of lithography. Then a photo-mask pattern on the ARC layer is formed to define trench regions, an anisotropic etching is performed to etch away unmasked portions of the nitride cap layer through the first polysilicon layer and slightly recess the silicon substrate using the patterned mask as a mask. After removing the patterned mask, a thermal annealed process is performed to grow a polyoxide layer on the sidewall of the first polysilicon layer and an thin oxynitride layer on the surface of the recessed silicon substrate. In the meantime, the buried bit lines are formed where each bit line is a layer beneath the first polysilicon layer. The trenches are then refilled with a silicon layer. A planarization process then follows. Subsequently, an interpoly dielectric layer is formed. Finally, a second polysilicon layer is formed and pattered to define word lines.

摘要翻译： 公开了一种用浅沟槽浮动栅极制造掩埋位线闪光EEROM单元以抑制短沟道效应的方法。 该方法包括以下步骤。 首先，在硅衬底上依次形成具有导电杂质的第一多晶硅层和氮化物覆盖层。 氮化物覆盖层用作抗反射涂层（ARC）层，用于提高光刻的分辨率。 然后形成ARC层上的光掩模图案以限定沟槽区域，执行各向异性蚀刻以蚀刻通过第一多晶硅层去除氮化物覆盖层的未屏蔽部分，并使用图案化掩模作为掩模稍微凹入硅衬底 。 在去除图案化掩模之后，进行热退火工艺以在第一多晶硅层的侧壁和凹入的硅衬底的表面上形成薄氧氮化物层上生长多氧化物层。 同时，形成掩埋位线，其中每个位线是第一多晶硅层下面的层。 然后用硅层重新填充沟槽。 然后，进行平面化处理。 接着，形成间隔电介质层。 最后，形成第二多晶硅层并图案化以限定字线。

公开(公告)号：US06207505B1

公开(公告)日：2001-03-27

申请号：US09326857

申请日：1999-06-07

申请人： Shye-Lin Wu

发明人： Shye-Lin Wu

IPC分类号： H01L21336

CPC分类号： H01L21/28273 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825

摘要： A method for fabricating a high-speed and high-density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. The pad oxide film is then removed. A polysilicon film is deposited over the substrate 2 and then oxidized into sacrificial oxide layer. After stripping the sacrificial oxide layer, a rugged topography is then formed on the doped substrate regions. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.

摘要翻译： 公开了一种用于制造高速和高密度非易失性存储单元的方法。 首先，制备具有限定的场氧化物和有源区的半导体衬底。 沉积堆叠的氧化硅/氮化硅层，然后定义隧道氧化物区域。 在非隧道区域上生长厚的氧化物。 在去除掩模氮化硅层之后，通过离子注入和热退火形成源极和漏极。 然后去除垫氧化膜。 多晶硅膜沉积在衬底2上，然后氧化成牺牲氧化物层。 在剥离牺牲氧化物层之后，在掺杂的衬底区域上形成粗糙的形貌。 此后，在粗糙的掺杂衬底区域上生长薄氧化物以形成坚固的隧道氧化物。 最后，依次形成浮栅，互补电介质和控制栅，并结束存储单元。

公开(公告)号：US06171893B2

公开(公告)日：2001-01-09

申请号：US09366606

申请日：1999-08-03

申请人： Shye-Lin Wu

发明人： Shye-Lin Wu

IPC分类号： H01L218238

CPC分类号： H01L21/823418 ,  H01L21/823443 ,  H01L21/823456 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0266

摘要： The method of forming MOS transistors includes the following steps. First, isolation regions are formed in the semiconductor substrate to separate the semiconductor substrate into an ESD protective region and a functional region. A gate insulator layer is formed on the substrate and a polysilicon layer is formed on the gate insulator layer. The polysilicon layer is then patterned to form gate structures on the ESD protective region and the functional region. The semiconductor substrate is doped for forming a first doped region and an insulator layer is formed over the semiconductor substrate. A portion of the insulator layer and a portion of the gate insulator layer are removed to form spacer structures and an insulator block. The semiconductor substrate is doped for forming a second doped region. An insulator opening is defined within the insulator block. The semiconductor substrate is then doped for forming a third doped region. In the preferred embodiments, the third doped region has opposite type dopants with the second doped region and the first doped region. A first thermal annealing is then performed to the semiconductor substrate to drive in dopants. A metal layer is then formed on the semiconductor substrate and a second thermal annealing is performed to the semiconductor substrate to form a metal silicide layer on the gate structures, and on the substrate over the second doped region and the third doped region. Finally, unreacted portions of the metal layer are removed.

摘要翻译： 形成MOS晶体管的方法包括以下步骤。 首先，在半导体衬底中形成隔离区以将半导体衬底分离成ESD保护区和功能区。 在衬底上形成栅极绝缘体层，并且在栅极绝缘体层上形成多晶硅层。 然后将多晶硅层图案化以在ESD保护区域和功能区域上形成栅极结构。 掺杂半导体衬底以形成第一掺杂区域，并且在半导体衬底上形成绝缘体层。 去除绝缘体层的一部分和栅极绝缘体层的一部分以形成间隔物结构和绝缘体块。 掺杂半导体衬底以形成第二掺杂区域。 绝缘体开口限定在绝缘体块内。 然后掺杂半导体衬底以形成第三掺杂区域。 在优选实施例中，第三掺杂区域具有与第二掺杂区域和第一掺杂区域相反的掺杂剂。 然后对半导体衬底进行第一热退火以在掺杂剂中驱动。 然后在半导体衬底上形成金属层，并对半导体衬底进行第二热退火，以在栅极结构上形成金属硅化物层，并在第二掺杂区域和第三掺杂区域上形成衬底。 最后，除去金属层的未反应部分。

公开(公告)号：US6137132A

公开(公告)日：2000-10-24

申请号：US109348

申请日：1998-06-30

申请人： Shye-Lin Wu

发明人： Shye-Lin Wu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The structure of flash EEPROM is formed on a composite substrate, wherein said composite substrate comprises: a pad oxide layer formed on a semiconductor substrate; an n-type doped dielectric layer is formed on the pad oxide layer. A nitride layer is formed on the n-type doped oxide layer. The composite substrate has a trench. An oxynitride layer which serves as coupling oxide layer is formed on surfaces of sidewalls and bottom of portion of the semiconductor substrate of the trench. The trench is filled with an n-type conductive doped polysilicon layer. The n-type conductive doped polysilicon layer serves as a floating gate of EEPROM. A conductive layer, a semiconductor substrate layer doped by using aforementioned n-type dopant containing oxide as a diffusion source, serves as buried bit lines being formed in the semiconductor substrate and abutting the pad oxide layer. An ONO layer is formed on the polysilicon layer and the nitride layer. Finally, another n+ conductive layer is formed on the ONO layer as word line.

摘要翻译： 闪存EEPROM的结构形成在复合衬底上，其中所述复合衬底包括：形成在半导体衬底上的衬垫氧化层; 在衬垫氧化物层上形成n型掺杂介质层。 在n型掺杂氧化物层上形成氮化物层。 复合衬底具有沟槽。 在沟槽的半导体衬底的部分的侧壁和底部的表面上形成用作耦合氧化物层的氧氮化物层。 沟槽填充有n型导电掺杂多晶硅层。 n型导电掺杂多晶硅层用作EEPROM的浮动栅极。 通过使用上述含有n型掺杂剂的氧化物作为扩散源掺杂的导电层，半导体衬底层用作在半导体衬底中形成并与衬垫氧化物层邻接的掩埋位线。 在多晶硅层和氮化物层上形成ONO层。 最后，在ONO层上形成另一个n +导电层作为字线。

公开(公告)号：US6130135A

公开(公告)日：2000-10-10

申请号：US81396

申请日：1998-05-18

申请人： Shye-Lin Wu

发明人： Shye-Lin Wu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/6656 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/42376

摘要： A method of fabricating a lightly doped drain transistor having an inverse-T gate structure. A semiconductor substrate is provided to implement said method. After a gate dielectric layer is formed on the substrate, the step of sequentially forming a first amorphous silicon layer and a second amorphous silicon layer follows. Then, the second amorphous silicon layer is patterned to form a first electrode, and first spacers are formed on sidewalls of the first electrode. Lightly-doped layers are thereafter formed in the substrate, and thus the first amorphous silicon layer is patterned to form a second electrode. Both steps make use of the first electrode and the first spacers as masking. Subsequently, second spacers are formed to overlie the first spacers and sidewalls of the second electrode. After heavily-doped layers are formed in the substrate by using the first electrode and the second spacers as masking, the lightly-doped layers are driven in so as to be fully covered by the second electrode.

摘要翻译： 一种制造具有逆T栅极结构的轻掺杂漏极晶体管的方法。 提供半导体衬底以实现所述方法。 在基板上形成栅介质层之后，依次形成第一非晶硅层和第二非晶硅层。 然后，对第二非晶硅层进行构图以形成第一电极，并且在第一电极的侧壁上形成第一间隔物。 此后在衬底中形成轻掺杂层，因此第一非晶硅层被图案化以形成第二电极。 两个步骤都利用第一电​​极和第一间隔物作为掩蔽。 随后，形成第二间隔物以覆盖第一间隔物和第二电极的侧壁。 在通过使用第一电极和第二间隔物作为掩模在衬底中形成重掺杂层之后，轻掺杂层被驱动以被第二电极完全覆盖。

公开(公告)号：US6117756A

公开(公告)日：2000-09-12

申请号：US336869

申请日：1999-06-18

申请人： Shye-Lin Wu

发明人： Shye-Lin Wu

IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L28/82 ,  H01L29/66825

摘要： The method for forming flash memory includes the following steps. At first, a semiconductor substrate with an isolation region formed thereupon is provided. The semiconductor substrate has a pad oxide layer and a first nitride layer formed thereover. A portion of the first nitride layer and a portion of the pad oxide layer are removed to define a gate region. A first oxide layer is formed and then a sidewall structure is formed. The semiconductor substrate is doped with first type dopants. A first thermal process is performed to form a second oxide layer and to drive in the first type dopants. The sidewall structure and the first nitride layer are then removed, and a first conductive layer is then formed over the substrate. A doping process is performed to dope the pad oxide layer, the first oxide layer, and the second oxide layer by implanting second type dopants through the first conductive layer. A second thermal process is performed and a portion of the first conductive layer is removed to define a floating gate. A dielectric layer is formed over the semiconductor substrate and a second conductive layer is then formed thereover as a control gate.

摘要翻译： 用于形成闪速存储器的方法包括以下步骤。 首先，提供其上形成有隔离区域的半导体衬底。 半导体衬底具有衬垫氧化物层和在其上形成的第一氮化物层。 第一氮化物层的一部分和衬垫氧化物层的一部分被去除以限定栅极区域。 形成第一氧化物层，然后形成侧壁结构。 半导体衬底掺杂有第一类型掺杂剂。 执行第一热处理以形成第二氧化物层并驱动第一类型掺杂剂。 然后去除侧壁结构和第一氮化物层，然后在衬底上形成第一导电层。 通过将第二类型掺杂剂注入第一导电层，进行掺杂工艺以掺杂衬垫氧化物层，第一氧化物层和第二氧化物层。 执行第二热处理，并且去除第一导电层的一部分以限定浮动栅极。 在半导体衬底上形成介电层，然后在其上形成第二导电层作为控制栅极。