发明授权
- 专利标题: Performance optimizing compiler for building a compiled SRAM
- 专利标题(中): 用于构建编译的SRAM的性能优化编译器
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申请号: US225075申请日: 1999-01-04
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公开(公告)号: US6002633A公开(公告)日: 1999-12-14
- 发明人: Jeffery H. Oppold , Michael R. Ouellette , Michael J. Sullivan
- 申请人: Jeffery H. Oppold , Michael R. Ouellette , Michael J. Sullivan
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: G11C8/12
- IPC分类号: G11C8/12 ; G11C8/00 ; G11C11/00
摘要:
A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.
公开/授权文献
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