发明授权
US6004849A Method of making an asymmetrical IGFET with a silicide contact on the
drain without a silicide contact on the source
失效
在漏极上制造具有硅化物接触的不对称IGFET的方法,而不在源极上具有硅化物接触
- 专利标题: Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source
- 专利标题(中): 在漏极上制造具有硅化物接触的不对称IGFET的方法,而不在源极上具有硅化物接触
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申请号: US911745申请日: 1997-08-15
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公开(公告)号: US6004849A公开(公告)日: 1999-12-21
- 发明人: Mark I. Gardner , Daniel Kadosh , Michael Duane
- 申请人: Mark I. Gardner , Daniel Kadosh , Michael Duane
- 申请人地址: CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: CA Sunnyvale
- 主分类号: H01L21/28
- IPC分类号: H01L21/28 ; H01L21/336 ; H01L29/78 ; H01L21/265
摘要:
A method of making an asymmetrical IGFET is disclosed. The method includes providing a semiconductor substrate with an active region, wherein the active region includes a source region and a drain region, forming a gate insulator on the active region, forming a gate on the gate insulator and over the active region, implanting arsenic into the active region to provide a greater concentration of arsenic in the source region than in the drain region, growing an oxide layer over the active region, wherein the oxide layer has a greater thickness over the source region than over the drain region due to the greater concentration of arsenic in the source region than in the drain region, forming a source in the source region and a drain in the drain region, depositing a refractory metal over the gate, the source, the drain, and the oxide layer, and reacting the refractory metal with the drain without reacting the refractory metal with the source, thereby forming a silicide contact on the drain without forming a silicide contact on the source. Advantageously, the IGFET has low source-drain resistance, shallow channel junctions, and an LDD that reduces hot carrier effects.
公开/授权文献
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