In a nonvolatile semiconductor memory device, flash memory cells are arranged in rows and columns and the individual memory cells 2nk are connected to word lines WLi and bit lines BLi. Further connected to the individual word lines WLi are verify cells 4n that are verified in place of the memory cells 2nk during the verification of the memory cells 2nk. The memory cells 2nk and verify cells 4n are formed into almost the same EEPROM structure having a floating electrode, except that the gate couple ratio of the verify cells 4n are set smaller than that of the gate couple ratio of the memory cells 2nk. Therefore, as long as electrons are injected sufficiently into these two types of cells, the threshold values of the verify cells 4n are always smaller than those of the memory cells 2nk. Consequently, when it is confirmed that the verify cells 4n have been verified, this means that the memory cells have been verified as well.