- 专利标题： Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions
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申请号： US59271申请日： 1998-04-10
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公开(公告)号： US6009506A公开(公告)日： 1999-12-28
- 发明人: Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
- 申请人： Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
- 申请人地址： CA Cupertino
- 专利权人： Tandem Computers Incorporated
- 当前专利权人： Tandem Computers Incorporated
- 当前专利权人地址： CA Cupertino
- 主分类号： G06F9/26
- IPC分类号： G06F9/26 ; G06F9/38
摘要：
A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.
公开/授权文献
- USD383946S Pumpkin bucket 公开/授权日：1997-09-23
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