In a data processing system, when a write mode register stores a delay information, a write data output signal generation unit delays an output start timing of write data by a predetermined time length, so that even if a just preceding read data exists on a data bus, the write data is outputted to the data bus after the just preceding read data has disappeared from the data bus. A write strobe signal generation unit makes an output timing of a write strobe signal in time with the output timing of the write data. Thus, it is possible to avoid collision between read data and write data without providing a special collision preventing buffer on the a data bus and without inserting a halt condition between a read cycle and a write cycle.