The present invention provides a flat display including a high-speed arithmetic logic facility so that, even when a data signal for a first line follows immediately after a frame start signal, the display displays an image with stable display quality quickly. For controlling driving signals in a flat display, each sub-frame of a temporally-segmented frame comprises at least an initialization period S1' during which a display screen is initialized, an addressing period S2 during which a plurality of cells are selected and written with display data, and a sustaining discharge period S3 during which the cells which contain display data are discharged so as to emit light for a given period of time. The flat display includes an initialization start time control unit 100 that detects the input of a display start signal V.sub.SYNC for one frame, and controls an initialization start time ST of the initialization period S1' so that the ST will precede an instant of input of a frame start signal V.sub.SYNC.