- 专利标题: Method of increasing capacitance of memory cells incorporating hemispherical grained silicon
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申请号: US650916申请日: 1996-05-17
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公开(公告)号: US6027970A公开(公告)日: 2000-02-22
- 发明人: Sujit Sharan , Thomas A. Figura , Anand Srinivasan , Gurtej S. Sandhu
- 申请人: Sujit Sharan , Thomas A. Figura , Anand Srinivasan , Gurtej S. Sandhu
- 申请人地址: ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: ID Boise
- 主分类号: H01L21/02
- IPC分类号: H01L21/02 ; H01L21/8242
摘要:
Disclosed is a method of increasing capacitance of a memory cell capacitor. A bottom electrode, comprising a hemispherical grained (HSG) silicon layer, is subjected to a dry etch process. The etch tends to separate the individual grains of the HSG silicon, thereby facilitating formation of a uniformly thick capacitor dielectric over the HSG silicon surface. Average thickness of the dielectric may therefore be reduced while maintaining reliability of the memory cell. The described embodiments include HCl/HF vapor etch, and NF.sub.3 plasma etch. Both of the preferred embodiments are configured to operate isotropically. Due to precisely controllable etch rates, the dry etch of the present invention is viable for separating grains of HSG silicon layers incorporated into extremely dense circuits (e.g., 64 Mbit DRAM) and correspondingly scaled down circuit dimensions.
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