Described herein is the converting between a component SDI signal D1 and a composite SDI signal D2. A single memory is prepared. Further, the corresponding signal is written into the memory in accordance with a clock corresponding to a transfer rate of the SDI signal D1 and the corresponding signal is read from the memory in accordance with a clock corresponding to a transfer rate of the SDI signal D2. The digital signal read from the memory is re-distributed based on header information added to the SDI signal D2. Pieces of header information (ADF, DID, DBN, DC and CS) corresponding to conversion modes are added to the outputted digital signal. Thus, the cost down to the signal converting can be achieved by providing a single signal conversion memory alone and reducing signal conversion memories and their peripheral circuits.