A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.