公开(公告)号：US08064257B2

公开(公告)日：2011-11-22

申请号：US12615502

申请日：2009-11-10

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G11C11/34

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

公开(公告)号：US07616485B2

公开(公告)日：2009-11-10

申请号：US11931881

申请日：2007-10-31

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

公开(公告)号：US06728138B2

公开(公告)日：2004-04-27

申请号：US10373872

申请日：2003-02-27

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G11C1606

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

公开(公告)号：US6031758A

公开(公告)日：2000-02-29

申请号：US125547

申请日：1998-12-23

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G06F11/20 ,  G11C7/00 ,  G11C11/34 ,  G11C16/06 ,  G11C29/00 ,  H04L12/28 ,  G11C16/04

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.

摘要翻译： PCT No.PCT / JP96 / 03501 Sec。 371日期1998年12月23日第 102（e）1998年12月23日PCT PCT 1996年11月29日PCT公布。 公开号WO97 / 32253 日期1997年9月4日具有电可擦除非易失性存储器的半导体存储器件，其中非易失性存储器具有用于各个块的管理信息区域和用于登记故障地址的故障登记区域。 如果一个块被访问并发现有故障，则执行故障登记，以便可以使用部分故障的存储器而不增加访问时间。 此外，通过在管理信息区域中一一对应地登记用于执行块的交换的管理信息地址，并且可以根据重写的频率来交换块。

公开(公告)号：US20080055986A1

公开(公告)日：2008-03-06

申请号：US11931881

申请日：2007-10-31

申请人： Kunihiro KATAYAMA ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro KATAYAMA ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G11C29/24

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

公开(公告)号：US06388920B2

公开(公告)日：2002-05-14

申请号：US09886133

申请日：2001-06-22

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G11C1606

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

公开(公告)号：US06317371B2

公开(公告)日：2001-11-13

申请号：US09824778

申请日：2001-04-04

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G11C700

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

公开(公告)号：US06236601B1

公开(公告)日：2001-05-22

申请号：US09477665

申请日：2000-01-05

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G11C700

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.

摘要翻译： 一种具有电可擦除非易失性存储器的半导体存储器件，其中非易失性存储器具有用于各个块的管理信息区域和用于登记故障地址的故障登记区域。 如果一个块被访问并发现有故障，则执行故障登记，以便可以使用部分故障的存储器而不增加访问时间。 此外，通过在管理信息区域中一一对应地登记用于执行块的交换的管理信息地址，并且可以根据重写的频率来交换块。

公开(公告)号：US08503235B2

公开(公告)日：2013-08-06

申请号：US13298548

申请日：2011-11-17

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G11C11/34 ,  G11C11/29

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

公开(公告)号：US20100177579A1

公开(公告)日：2010-07-15

申请号：US12615502

申请日：2009-11-10

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G11C29/04

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。