A digital pulse delay system comprises: a counter incremented responsive to a succession of input pulses and generating a plurality of successive gating signals; a plurality of gates, each having a first input for receiving said input pulses and a second input the receiving a different one of said gating signals; a plurality of pulse delay circuits providing uniform time delays, each receiving an output pulse from a different one of said gates; and, an output circuit combining said uniformly delayed pulses from all of said delay circuits into a single output signal representing a uniformly delayed version of said succession of input pulses. A method for digitally delaying a signal of spaced pulses comprises the steps of: digitally generating a control sequence responsive to said spaced pulses; successively and uniformly digitally delaying successive ones of said spaced pulses in parallel, responsive to said control sequence; and, digitally combining said uniformly delayed pulses into a single output signal representing a uniformly delayed version of said digital signal.