For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.