A shallow junction MOS transistor comprising a semiconductor substrate having an upper region that includes a first and a second lightly doped region laterally displaced on either side of the channel region. The first and second lightly doped regions extend to a junction depth below the upper surface of the semiconductor substrate. A first and a second lightly doped impurity distribution are located within the first and second source/drain regions of the semiconductor substrate. The shallow junction transistor further includes a gate dielectric formed on an upper surface of the channel region of the semiconductor substrate. A conductive gate that includes a first and a second sidewall is formed on the gate dielectric. A gate insulator is formed in contact with the first and second sidewalls of the conductive gate. First and second source/drain structures are formed above the upper surface of the semiconductor substrate. The first and second source/drain structures are laterally displaced over the first and second lightly doped regions of the semiconductor substrate.