- 专利标题： Graded LDD implant process for sub-half-micron MOS devices
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申请号： US949997申请日： 1997-10-14
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公开(公告)号： US6046472A公开(公告)日： 2000-04-04
- 发明人: Aftab Ahmad , Charles Dennison
- 申请人： Aftab Ahmad , Charles Dennison
- 申请人地址： ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： ID Boise
- 主分类号： H01L21/28
- IPC分类号： H01L21/28 ; H01L21/336 ; H01L21/8238 ; H01L29/10 ; H01L29/78 ; H01L29/784
摘要：
A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.
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