A current processing circuit having reduced charge and discharge time constant errors caused by variations in operating temperature and voltage while conveying charge and discharge currents to and from a capacitor, respectively. Instead of switching both the charge and discharge currents on and off, only the charge current is switched. The discharge current, generated and sunk by a current mirror circuit, remains on at all times. The charge current is two times the nominal discharge current. The actual discharge current is the sum of the nominal, or desired, discharge current, plus a small error current component introduced by the current mirror circuit generating the discharge current (thereby making the charge current approximately two times the actual discharge current). Alternatively, the discharge current can be switched while the charge current, generated and sourced by a current mirror circuit, remains on at all times. The discharge current is two times the nominal charge current. The actual charge current is the sum of the nominal, or desired, charge current, plus a small error current component introduced by the current mirror circuit generating the charge current (thereby making the discharge current approximately two times the actual charge current). As a result, the charging and discharging time constants of the capacitor are significantly less dependent upon operating temperature and voltage.