Methods and circuits for triggering column select line for write operations in a multiple data rate (e.g., a double data rate) operation. A memory device includes a memory array that stores data values, an address logic circuit that generates an address for the memory array, and a column decoder. The column decoder couples to the address logic circuit and the memory array. The column decoder receives either a data strobe input signal (DQS) or a clock signal (CLK), or both, and activates a column select line for the memory array in response to one of the input signal(s).