- 专利标题: Semiconductor IC device having a memory and a logic circuit implemented with a single chip
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申请号: US813900申请日: 1997-03-07
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公开(公告)号: US6069834A公开(公告)日: 2000-05-30
- 发明人: Takao Watanabe , Kazushige Ayukawa , Ryo Fujita , Kazumasa Yanagisawa , Hitoshi Tanaka
- 申请人: Takao Watanabe , Kazushige Ayukawa , Ryo Fujita , Kazumasa Yanagisawa , Hitoshi Tanaka
- 申请人地址: JPX Tokyo JPX Tokyo
- 专利权人: Hitachi, Ltd.,Hitachi Ulsi Engineering Corporation
- 当前专利权人: Hitachi, Ltd.,Hitachi Ulsi Engineering Corporation
- 当前专利权人地址: JPX Tokyo JPX Tokyo
- 优先权: JPX8-051321 19960308; JPX8-051330 19960308; JPX8-147010 19960610; JPX8-301538 19961113
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G11C7/00 ; G11C7/02 ; G11C7/10 ; G11C8/12 ; H01L27/108 ; G11C8/00
摘要:
A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.
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