发明授权
US6070203A Circuit for generating almost full and almost empty flags in response to
sum and carry outputs in asynchronous and synchronous FIFOS
有权
用于响应于和产生几乎完全和几乎空的标志的电路,并在异步和同步FIFOS中传送输出
- 专利标题: Circuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOS
- 专利标题(中): 用于响应于和产生几乎完全和几乎空的标志的电路,并在异步和同步FIFOS中传送输出
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申请号: US201413申请日: 1998-11-30
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公开(公告)号: US6070203A公开(公告)日: 2000-05-30
- 发明人: Andrew L. Hawkins , Pidugu L. Narayana
- 申请人: Andrew L. Hawkins , Pidugu L. Narayana
- 申请人地址: CA San Jose
- 专利权人: Cypress Semiconductor Corp.
- 当前专利权人: Cypress Semiconductor Corp.
- 当前专利权人地址: CA San Jose
- 主分类号: G06F5/10
- IPC分类号: G06F5/10 ; G06F5/12 ; G06F13/14
摘要:
An efficient design to generate a programmable almost empty or programmable almost full flags. The present invention accomplishes this by efficiently evaluating the read count minus write count plus a user programmed offset being greater than or equal to zero for the programmable almost empty flag generation. Similarly, evaluating write count minus the read count plus the user programmed offset minus the size of the FIFO is greater than or equal to zero for the programmable almost full flag generation. The counters in the FIFO count from 0 to twice the size of the FIFO minus one and the user programmed offset can be between 0 to the size of the FIFO minus one. The offset has one less bit than the read and write counters. The processing block masks out the higher order bits of the Offset input based on the size of the FIFO. The first stage performs the bit wise addition of the offset, read counter and write counter inputs without any carry chain propagation. From the sum and carry outputs of the first stage bitwise addition, bits with equal weights are united and the overall carry out of this addition is generated very efficiency. The overall carry represents the external almost empty or almost full flag.
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