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公开(公告)号：US06731566B1
公开(公告)日：2004-05-04
申请号：US09876429
申请日：2001-06-06
IPC分类号： G11C1141
CPC分类号： G11C8/16 , G11C7/1075 , G11C11/412
摘要： In a single ended simplex dual port memory cell, one port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.
摘要翻译： 在单端单工双端口存储单元中，存储单元的一个端口专用于写操作，而存储单元的另一个端口专用于读操作。 从第一端口接收到的数据位可以存储在存储单元中。 第二端口可以基本上同时检测存储器单元的内容，因为存储器单元正在存储来自第一端口的一位数据。 每个端口都针对其各自的专用操作进行了优化。 换句话说，一个端口针对写入操作进行了优化，另一个端口针对读取操作进行了优化。 因为存储器单元的一个端口被优化用于写入操作，并且存储器单元的另一端口被优化用于读取操作，所以单元不需要用于每个端口的多个字线电压。
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2.发明授权Clocking scheme for independently reading and writing multiple width words from a memory array 失效用于独立地从存储器阵列读取和写入多个宽度字的时钟方案公开(公告)号：US06510486B1
公开(公告)日：2003-01-21
申请号：US08621487
申请日：1996-03-25
IPC分类号： G06F1200
CPC分类号： G06F5/10 , G06F5/00 , G11C7/1018 , G11C7/103 , G11C7/1075
摘要： The present invention provides a circuit for writing a particular sized data word from a common input to a number of individual memory cells in a memory array and reading a particular sized data word from the individual memory cells to a common output. The size of the word written to the memory cells can be larger, smaller or the same as the size of the word read from the memory array. The present invention uses a multi-bit write counter to distribute a write timing signal to a number of multiplexer blocks and a multi-bit read counter to distribute a read timing signal to a number of sense amplifier blocks. Each of the multiplexer blocks receives both a data input signal from the common input and the write timing signal continuously when the circuit is in operation. Each of the sense amplifier blocks receives data from the memory array and a read timing signal at all times. When a particular read timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from one or more of the corresponding memory arrays and is presented to the common output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to both read and write multiple width words to and from the memory array.
摘要翻译： 本发明提供了一种用于将特定大小的数据字从公共输入写入存储器阵列中的多个单独存储器单元并且将特定大小的数据字从各个存储器单元读取到公共输出的电路。 写入存储器单元的字的大小可以比从存储器阵列读取的字的大小更小或相同。 本发明使用多比特写计数器将写定时信号分配给多个多路复用器块和多比特读计数器，以将读定时信号分配到多个读出放大器块。 当电路运行时，多路复用器块中的每一个都接收来自公共输入端的数据输入信号和写定时信号。 每个读出放大器块一直从存储器阵列接收数据和读取定时信号。 当特定的读定时信号存在于读出放大器时，从一个或多个对应的存储器阵列接收包含固定宽度数据字的输出信号，并将其呈现给公共输出。 本发明减少了实现控制功能所需的内部信号线的数量，并且允许容易地对存储器阵列的读取和写入多个宽度字进行修改。
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3.发明授权Circuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOS 有权用于响应于和产生几乎完全和几乎空的标志的电路，并在异步和同步FIFOS中传送输出
公开(公告)号：US6070203A
公开(公告)日：2000-05-30
申请号：US201413
申请日：1998-11-30
CPC分类号： G06F5/12 , G06F2205/126
摘要： An efficient design to generate a programmable almost empty or programmable almost full flags. The present invention accomplishes this by efficiently evaluating the read count minus write count plus a user programmed offset being greater than or equal to zero for the programmable almost empty flag generation. Similarly, evaluating write count minus the read count plus the user programmed offset minus the size of the FIFO is greater than or equal to zero for the programmable almost full flag generation. The counters in the FIFO count from 0 to twice the size of the FIFO minus one and the user programmed offset can be between 0 to the size of the FIFO minus one. The offset has one less bit than the read and write counters. The processing block masks out the higher order bits of the Offset input based on the size of the FIFO. The first stage performs the bit wise addition of the offset, read counter and write counter inputs without any carry chain propagation. From the sum and carry outputs of the first stage bitwise addition, bits with equal weights are united and the overall carry out of this addition is generated very efficiency. The overall carry represents the external almost empty or almost full flag.
摘要翻译： 一个高效的设计来生成一个可编程的几乎空的或可编程的几乎全标志。 本发明通过有效地评估对于可编程的几乎空标志生成，读取计数减写入计数加上大于或等于零的用户编程偏移量来实现。 类似地，对于可编程的几乎全标志生成，评估写入计数减去读取计数加上用户编程的偏移减去FIFO的大小大于或等于零。 FIFO中的计数器从0到2倍于FIFO的大小减去1，用户编程的偏移可以在0到FIFO的大小减去1之间。 偏移量比读写计数器少一位。 处理块根据FIFO的大小屏蔽偏移输入的高位。 第一级执行偏移，读取计数器和写入计数器输入的逐位添加，而不需要任何进位链传播。 从第一级逐位加法的和和进位输出中，将具有相等权重的位相结合，并且总体执行该加法非常有效率地产生。 总体进位代表外部几乎空或几乎全旗。
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公开(公告)号：US6023435A
公开(公告)日：2000-02-08
申请号：US995381
申请日：1997-12-22
CPC分类号： G11C7/12
摘要： A circuit and method for staggering a bitline precharge between particular sections of a memory array. The present invention may be implemented in memories having increasing depths to reduce unacceptably high precharge current requirements associated with high bitline loads. Since the particular memory sections of the memory array are turned on independently, the peak current necessary to charge the particular bitlines is limited. The present invention may be implemented in logic and may therefore be less sensitive to process and temperature variations.
摘要翻译： 一种用于在存储器阵列的特定部分之间交错位线预充电的电路和方法。 本发明可以在具有增加的深度的存储器中实现，以减少与高位线负载相关联的不可接受的高预充电电流要求。 由于存储器阵列的特定存储器部分独立地导通，所以对特定位线充电所需的峰值电流是有限的。 本发明可以以逻辑实现，因此可能对过程和温度变化较不敏感。
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5.发明授权
公开(公告)号：US5852748A
公开(公告)日：1998-12-22
申请号：US578209
申请日：1995-12-29
CPC分类号： G06F5/10
摘要： The present invention provides a circuit for generating a programmable write-read word line equality signal in FIFO buffers. The present invention significantly reduces the gate delay associated in producing the write-read word line equality signal. The delay is reduced from a typical 30-50 gate delays, to as little as four gate delays. The present invention accomplishes this by processing several bit operations in parallel and making the general circuit architecture symmetric. The delay is constant in all of the parallel paths but amounts to only a short delay for the final WREQ output.
摘要翻译： 本发明提供了一种用于在FIFO缓冲器中产生可编程写入读取字线相等信号的电路。 本发明显着地减少了与产生写入读取字线相等信号相关联的门延迟。 延迟从典型的30-50门延迟减少到只有四个门延迟。 本发明通过并行处理几位操作并使通用电路架构对称来实现。 所有并行路径的延迟是恒定的，但对于最终的WREQ输出而言，延迟仅为短暂的延迟。
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公开(公告)号：US5751644A
公开(公告)日：1998-05-12
申请号：US756634
申请日：1996-11-26
IPC分类号： B01F7/00 , G11C11/407
CPC分类号： G11C7/1087 , G11C7/1093 , G11C7/1096
摘要： The present invention concerns data transition method and apparatus for driving a set of write data signals to an inactive (or deasserted) state upon completion of a WRITE to a particular group of memory cells. The present invention drives the write data signals to a an inactive state to end a WRITE without waiting for the end of the write control pulse. The present invention triggers a group of data write buffers to drive one of the write data signals to a "0" at the beginning of the WRITE control pulse or at a data input transition during a WRITE. A delayed transition of the write data signals may be used to drive both the write data signals to a "1"� to end the WRITE within a particular memory group. The write data transition detection is accomplished at the write data inputs of the groups of memory cells without relying on global chip data input pin transition detection and pulse width setting. The data setup to the end of WRITE is generally not compromised since the path from chip data input to the input to the write data signals is generally similar to existing implementations.
摘要翻译： 本发明涉及数据转换方法和装置，用于在完成对特定组存储器单元的写入时将一组写入数据信号驱动到无效（或无效）状态。 本发明将写入数据信号驱动到非活动状态以结束写入而不等待写入控制脉冲的结束。 本发明触发一组数据写入缓冲器，以在WRITE控制脉冲开始时或写入期间的数据输入转换时将写数据信号之一驱动为“0”。 可以使用写入数据信号的延迟转换来将写入数据信号驱动为“1”|以结束特定存储器组中的写入。 在不依赖于全局芯片数据输入引脚转换检测和脉冲宽度设置的情况下，在存储器单元组的写入数据输入端实现写入数据转换检测。 由于从芯片数据输入到输入到写入数据信号的路径通常与现有实现相似，因此通常不会影响写入结束的数据设置。
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公开(公告)号：US5627797A
公开(公告)日：1997-05-06
申请号：US572623
申请日：1995-12-14
CPC分类号： G06F5/14 , G06F5/06 , G06F5/12 , G06F2205/126
摘要： The invention describes an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.
摘要翻译： 本发明描述了一种具有可编程tSKEW的异步状态机，其用于在同步FIFO缓冲器中产生空和满标志。 本发明减少了从典型的八个门延迟产生全标志或空标志相关的延迟，甚至没有门延迟。 本发明通过使用只能使内部标志变为低电平或有效的设定状态机和只能使内部标志变高或不活动的复位状态机来实现。 设置状态机和复位状态机的功能由阻塞逻辑控制。 每个状态机的输出被存储在锁存器中。 锁存器的输出被呈现给阻塞逻辑的输入，该阻塞逻辑由阻塞逻辑用于控制状态机的活动。
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公开(公告)号：US06262912B1
公开(公告)日：2001-07-17
申请号：US09443062
申请日：1999-11-18
IPC分类号： G11C1100
CPC分类号： G11C8/16 , G11C11/412
摘要： A single ended simplex dual port memory cell is described. One port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.
摘要翻译： 描述了单端单工双端口存储器单元。 存储器单元的一个端口专用于写入操作，并且存储器单元的另一个端口专用于读取操作。 从第一端口接收到的数据位可以存储在存储单元中。 第二端口可以基本上同时检测存储器单元的内容，因为存储器单元正在存储来自第一端口的一位数据。 每个端口都针对其各自的专用操作进行了优化。 换句话说，一个端口针对写入操作进行了优化，另一个端口针对读取操作进行了优化。 因为存储器单元的一个端口被优化用于写入操作，并且存储器单元的另一端口被优化用于读取操作，所以单元不需要用于每个端口的多个字线电压。
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9.发明授权Circuit having plurality of carry/sum adders having read count, write count, and offset inputs to generate an output flag in response to FIFO fullness 失效具有多个具有读取计数，写入计数和偏移输入的进位/加法加法器的电路，以响应于FIFO充满度而产生输出标志
公开(公告)号：US5850568A
公开(公告)日：1998-12-15
申请号：US577712
申请日：1995-12-22
CPC分类号： G06F5/12 , G06F2205/126
摘要： The present invention provides an efficient design that can be used to generate a programmable almost empty or programmable almost full flags. The present invention accomplishes this by efficiently evaluating the read count minus write count plus a user programmed offset being greater than or equal to zero for the programmable almost empty flag generation. Similarly, evaluating write count minus the read count plus the user programmed offset minus the size of the FIFO is greater than or equal to zero for the programmable almost full flag generation. The counters in the FIFO count from 0 to twice the size of the FIFO minus one and the user programmed offset can be between 0 to the size of the FIFO minus one. The offset has one less bit than the read and write counters. The processing block masks out the higher order bits of the Offset input based on the size of the FIFO. The first stage performs the bit wise addition of the offset, read counter and write counter inputs without any carry chain propagation. From the sum and carry outputs of the first stage bitwise addition, bits with equal weights are united and the overall carry out of this addition is generated very efficiency. The overall carry represents the external almost empty or almost full flag.
摘要翻译： 本发明提供了一种有效的设计，可用于生成可编程的几乎空的或可编程的几乎全标志。 本发明通过有效地评估对于可编程的几乎空标志生成，读取计数减写入计数加上大于或等于零的用户编程偏移量来实现。 类似地，对于可编程的几乎全标志生成，评估写入计数减去读取计数加上用户编程的偏移减去FIFO的大小大于或等于零。 FIFO中的计数器从0到2倍于FIFO的大小减去1，用户编程的偏移可以在0到FIFO的大小减去1之间。 偏移量比读写计数器少一位。 处理块根据FIFO的大小屏蔽偏移输入的高位。 第一级执行偏移，读取计数器和写入计数器输入的逐位添加，而不需要任何进位链传播。 从第一级逐位加法的和和进位输出中，将具有相等权重的位相结合，并且总体执行该加法非常有效率地产生。 总体进位代表外部几乎空或几乎全旗。
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10.发明授权Decoder circuit and method for disabling a number of columns or rows in a memory 失效解码器电路和用于禁用存储器中的多个列或行的方法
公开(公告)号：US5828624A
公开(公告)日：1998-10-27
申请号：US772497
申请日：1996-12-23
CPC分类号： G11C29/785 , G11C29/80 , G11C29/812
摘要： The present invention concerns a method and apparatus for disabling columns using a local fuse decoding system. The present invention uses local decoding in order to use a number of fuses that is less than the number of columns in order to disable column failures. This is particularly useful when the fuse pitch is greater than the column pitch which does not allow for a fuse to be implemented in each column.
摘要翻译： 本发明涉及一种使用本地熔丝解码系统禁用列的方法和装置。 本发明使用本地解码，以便使用小于列数的多个熔丝以便禁止列故障。 当保险丝间距大于不允许在每列中实现保险丝的列间距时，这是特别有用的。
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