发明授权
- 专利标题： Bus arbiter operable as a DRAM controller
- 专利标题（中）： 总线仲裁器可操作为DRAM控制器
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申请号： US996317申请日： 1997-12-22
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公开(公告)号： US6070212A公开(公告)日： 2000-05-30
- 发明人: Midori Yasuda , Masashi Kamada , Takayuki Ninomiya , Kazuhiko Morimura
- 申请人： Midori Yasuda , Masashi Kamada , Takayuki Ninomiya , Kazuhiko Morimura
- 申请人地址： JPX Tokyo
- 专利权人： Canon Kabushiki Kaisha
- 当前专利权人： Canon Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX8-356504 19961226
- 主分类号： G06F13/16
- IPC分类号： G06F13/16 ; G06F13/362 ; G06F13/00
摘要：
A bus arbiter capable of avoiding needless increase in circuit scale is provided. The bus arbiter controls a bus shared by a CPU (central processing unit) and a plurality of apparatuses for generating addresses. The bus arbiter includes a determination unit for determining if a request of an address is a request of an address where no corresponding device is present, and a processor for passing the request by transmitting an ACK signal without performing a writing operation for a request of a writing operation, and transmitting dummy data and an ACK signal without performing a reading operation for a request of a reading operation, when the determination unit has determined that the request is a request of an address where no corresponding device is present.