发明授权
- 专利标题: Partial silicidation method to form shallow source/drain junctions
- 专利标题(中): 部分硅化法形成浅源极/漏极结
-
申请号: US23383申请日: 1998-02-13
-
公开(公告)号: US6071782A公开(公告)日: 2000-06-06
- 发明人: Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
- 申请人: Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
- 申请人地址: WA Camas JPX Osaka
- 专利权人: Sharp Laboratories of America, Inc.,Sharp Kabushiki Kaisha
- 当前专利权人: Sharp Laboratories of America, Inc.,Sharp Kabushiki Kaisha
- 当前专利权人地址: WA Camas JPX Osaka
- 主分类号: H01L21/28
- IPC分类号: H01L21/28 ; H01L21/285 ; H01L21/336 ; H01L21/60 ; H01L29/78 ; H01L21/44
摘要:
A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.
公开/授权文献
- USD362097S Kiosk 公开/授权日:1995-09-05
信息查询
IPC分类: