发明授权
US06073213A Method and apparatus for caching trace segments with multiple entry
points
失效
用于缓存具有多个入口点的跟踪段的方法和装置
- 专利标题: Method and apparatus for caching trace segments with multiple entry points
- 专利标题(中): 用于缓存具有多个入口点的跟踪段的方法和装置
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申请号: US982097申请日: 1997-12-01
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公开(公告)号: US06073213A公开(公告)日: 2000-06-06
- 发明人: Guy Peled , Robert C. Valentine , Oded Lempel
- 申请人: Guy Peled , Robert C. Valentine , Oded Lempel
- 申请人地址: CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: G06F9/38
- IPC分类号: G06F9/38 ; G06F12/08
摘要:
An apparatus includes a data array and control logic. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The control logic allows the instructions of the trace segment to be sequentially retrieved beginning with a selected instruction. The selected instruction is offset from the first instruction of the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A selected instruction of the first plurality of instructions is identified within the first trace segment. The selected instruction is offset from the first instruction of the first trace segment. The offset information related to the position of the selected instruction within the first trace segment is stored. A method for retrieving cached instructions, wherein the cached instructions are stored in a trace segment and the trace segment has a head instruction, includes determining a linear address related to a selected instruction to be retrieved. An entry point into the trace segment corresponding to the linear address is identified. The entry point is offset from the head instruction. The selected instruction is retrieved from the entry point within the identified trace segment.
公开/授权文献
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