A host module (2) including a host CPU (10) and a configurable expansion bus controller (28, 28', 128) is disclosed. The expansion bus controller (28, 28', 128) is configurable by way of configuration signals (BCFG) to be operable in various bus configurations for communicating signals between a module bus (IBUS) and external buses (XPCI1, XPCI0). These modes include combining the external buses (XPCI1, XPCI0) into a single bus of the 64-bit PCI type, operating the external buses (XPCI1, XPCI0) as separate 32-bit PCI buses, as separate CardBus buses, as separate AGP buses (either at one or multiple data transfers per cycle), or as combinations thereof. Certain of the configuration signals (BCFG) are used to select the clock frequencies at which the external buses (XPCI1, XPCI0) operate, in either of the 64-bit or 32-bit PCI protocols, or in the AGP bus protocol when present. The external buses (XPCI1, XPCI0) may be operable at different speeds, and at different protocols, depending upon the state of the configuration signals (BCFG).