A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.