公开(公告)号：US6038674A

公开(公告)日：2000-03-14

申请号：US352343

申请日：1999-07-13

申请人： Takatsugu Sasaki ,  Akira Kabemoto ,  Hirohide Sugahara ,  Junji Nishioka ,  Satoshi Shinohara ,  Yozo Nakayama ,  Jun Sakurai ,  Naohiro Shibata ,  Toshiyuki Muta ,  Takayuki Shimamura

发明人： Takatsugu Sasaki ,  Akira Kabemoto ,  Hirohide Sugahara ,  Junji Nishioka ,  Satoshi Shinohara ,  Yozo Nakayama ,  Jun Sakurai ,  Naohiro Shibata ,  Toshiyuki Muta ,  Takayuki Shimamura

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0813 ,  G06F12/0808

摘要： A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

摘要翻译： 多处理器，其中多个处理器经由系统总线连接。 多处理器包括每个具有至少一个处理器，主存储器，高速缓冲存储器，高速缓存控制单元，目录存储器和目录控制单元的处理器组。 目录控制单元包括无效命令发布单元，其向存储在高速缓存行中的目录存储器中的所有参考指定发出高速缓存行无效命令。 因此，可以通过减少从缓存存储器发出高速缓存无效命令的频率来缩短设备处理时间。

公开(公告)号：US20060002399A1

公开(公告)日：2006-01-05

申请号：US10997950

申请日：2004-11-29

申请人： Toshiyuki Muta

发明人： Toshiyuki Muta

IPC分类号： H04L12/28

CPC分类号： G06F13/4054 ,  H03L7/06 ,  H04J3/0629 ,  H04L7/005

摘要： A data reception apparatus adjusts a first clock signal and fetches the data signal in a data buffer, using a data signal in accordance with the adjustment clock signal in such a way that a set-up time and a hold time of the data signal are secured for each bit or for each group of parallel data. Then, this apparatus selects the data of a plurality of bits in the data buffer in chronological order and reads out the selected data as parallel data, in accordance with a second clock signal.

公开(公告)号：US06708294B1

公开(公告)日：2004-03-16

申请号：US09696029

申请日：2000-10-26

申请人： Manabu Nakao ,  Toshiyuki Muta ,  Makoto Hataida

发明人： Manabu Nakao ,  Toshiyuki Muta ,  Makoto Hataida

IPC分类号： H02H305

CPC分类号： G06F12/126 ,  G06F11/1064 ,  G06F12/0804 ,  G06F12/0897 ,  G06F2212/1032

摘要： A cache memory apparatus includes a primary cache memory using a 4-way set associative method and a secondary cache memory. When a parity error occurs in an entry in the primary cache memory, the way is prohibited from being replaced, and data related to the entry is written back from the primary cache memory to the secondary cache memory. Thereafter, the entry in the primary cache memory is made invalid, and the prohibition on the replacement of the way is released. When the secondary cache memory is accessed, the data written back is moved from the secondary cache memory to the entry into the primary cache memory to set a status before the parity error occurs.

摘要翻译： 高速缓冲存储器装置包括使用4路组关联方法和次级高速缓冲存储器的主高速缓冲存储器。 当主缓冲存储器中的条目发生奇偶校验错误时，禁止替换该方法，并将与该条目相关的数据从主缓存存储器写回到次级高速缓冲存储器。 此后，使一级高速缓冲存储器中的条目成为无效，并且释放对该方式的更换的禁止。 当二次缓存存储器被访问时，回写的数据从次级高速缓冲存储器移动到主高速缓冲存储器的条目，以在发生奇偶校验错误之前设置状态。

公开(公告)号：US06681294B1

公开(公告)日：2004-01-20

申请号：US09537354

申请日：2000-03-29

申请人： Shinya Kato ,  Toshiyuki Muta

发明人： Shinya Kato ,  Toshiyuki Muta

IPC分类号： G06F1208

CPC分类号： G06F12/0864 ,  G06F12/0862

摘要： A cache control apparatus for an information processing system having a cache memory with a plurality of ways is disclosed, in which the hardware amount is reduced and the delay of the response time is minimized. At the time of cache access, each way is indexed by time division, and when updating the cache, a way to be updated is designated thereby to update the cache tag and the cache data. The data indexed by time division can be judged for a hit each time of indexing or alternatively, the data of all the ways are judged for a hit after being held in a buffer. The data indexed by time division is sent to the reader as response without regard to the way, and when a miss is judged, a cancel signal is sent thereby to minimize the access time delay. Further by predicting the address of a way, the access time can be further improved.

摘要翻译： 公开了一种具有多路方式的具有高速缓存存储器的信息处理系统的高速缓存控制装置，其中硬件量减少，并且响应时间的延迟最小化。 在缓存访问时，通过时分方式对每个方式进行索引，并且当更新缓存时，指定要更新的方式，从而更新高速缓存标签和高速缓存数据。 通过分时索引的数据可以针对每次索引的命中来判断，或者替换地，在保持在缓冲器中之后，所有方式的数据被判断为命中。 通过时分索引的数据被作为响应发送给读取器，而不考虑方式，并且当判断出未命中时，发送取消信号从而最小化访问时间延迟。 此外，通过预测方式的地址，可以进一步提高访问时间。

公开(公告)号：US06442665B2

公开(公告)日：2002-08-27

申请号：US09753563

申请日：2001-01-04

申请人： Makoto Hataida ,  Toshiyuki Muta

发明人： Makoto Hataida ,  Toshiyuki Muta

IPC分类号： G06F1200

CPC分类号： G06F12/1054 ,  G06F12/0859

摘要： A calculating part performs calculation. A storing part stores data from the calculating part. An address converting part converts an address corresponding to data requested by the calculating part. A first comparing part compares an address from the address converting part and data stored in the storing part. A second comparing part compares the address corresponding to the data requested by the calculating part with an address of said storing part. A selecting part selects the data stored in the storing part to be provided to the calculating part when an address comparison result of the first comparing part is coincidence and also an address comparison result of the second comparing part is coincidence.

摘要翻译： 计算部分进行计算。 存储部存储来自计算部的数据。 地址转换部分转换与计算部分请求的数据相对应的地址。 第一比较部分比较来自地址转换部分的地址和存储在存储部分中的数据。 第二比较部分将与计算部分请求的数据对应的地址与所述存储部分的地址进行比较。 当第一比较部分的地址比较结果一致时，选择部分选择存储在要提供给计算部分的存储部分中的数据，并且第二比较部分的地址比较结果是一致的。

公开(公告)号：US07620138B2

公开(公告)日：2009-11-17

申请号：US10997950

申请日：2004-11-29

申请人： Toshiyuki Muta

发明人： Toshiyuki Muta

IPC分类号： H04L7/00

CPC分类号： G06F13/4054 ,  H03L7/06 ,  H04J3/0629 ,  H04L7/005

摘要： A data reception apparatus adjusts a first clock signal and fetches the data signal in a data buffer, using a data signal in accordance with the adjustment clock signal in such a way that a set-up time and a hold time of the data signal are secured for each bit or for each group of parallel data. Then, this apparatus selects the data of a plurality of bits in the data buffer in chronological order and reads out the selected data as parallel data, in accordance with a second clock signal.

摘要翻译： 数据接收装置利用数据信号调整第一时钟信号并在数据缓冲器中取出数据信号，使得数据信号的建立时间和保持时间得以保证 对于每个位或每组并行数据。 然后，该装置按照时间顺序选择数据缓冲器中的多个位的数据，并根据第二时钟信号读出所选择的数据为并行数据。

公开(公告)号：US06772297B2

公开(公告)日：2004-08-03

申请号：US09817258

申请日：2001-03-27

申请人： Toshiyuki Muta

发明人： Toshiyuki Muta

IPC分类号： G06F1208

CPC分类号： G06F9/383 ,  G06F12/0862

摘要： To perform a data replace control activated prior to the execution of a cache memory reference instruction so as to reduce the latency when a miss occurs to a cache memory. In a cache replace control of a load store unit, a load store unit controlling device comprises a first queue selection logical circuit 41, a second queue selection logical circuit 42 and a mediating unit 43, wherein the first queue selection logical circuit sequentially selects access instructions to access the cache memory which are stored in queues 31, wherein the second queue selection logical circuit selects unissued access instructions of the access instructions to access the cache memory which are stored in the queues prior to the selections by the first queue selection logical circuit, and wherein the mediating unit mediates between the access instructions selected by the first queue selection logical circuit and the pre-access instructions selected by the second queue selection logical circuit for accessing the cache memory.

摘要翻译： 执行在执行高速缓存存储器参考指令之前激活的数据替换控制，以便在高速缓存存储器发生未命中时减少等待时间。在加载存储单元的高速缓存替换控制中，加载存储单元控制设备包括 第一队列选择逻辑电路41，第二队列选择逻辑电路42和中介单元43，其中第一队列选择逻辑电路顺序地选择访问存储在队列31中的高速缓存存储器的访问指令，其中第二队列选择逻辑 电路选择访问指令的未发布访问指令，以访问在由第一队列选择逻辑电路进行选择之前存储在队列中的高速缓冲存储器，并且其中中介单元在由第一队列选择逻辑电路选择的访问指令之间进行中介 以及由第二队列选择逻辑电路选择的用于访问的预访问指令 缓存内存。

公开(公告)号：US6092173A

公开(公告)日：2000-07-18

申请号：US824871

申请日：1997-03-26

申请人： Takatsugu Sasaki ,  Akira Kabemoto ,  Hirohide Sugahara ,  Junji Nishioka ,  Yozo Nakayama ,  Jun Sakurai ,  Toshiyuki Muta ,  Takayuki Shimamura

发明人： Takatsugu Sasaki ,  Akira Kabemoto ,  Hirohide Sugahara ,  Junji Nishioka ,  Yozo Nakayama ,  Jun Sakurai ,  Toshiyuki Muta ,  Takayuki Shimamura

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0813 ,  G06F12/0808

摘要： A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

公开(公告)号：US5890217A

公开(公告)日：1999-03-30

申请号：US598243

申请日：1996-02-07

申请人： Akira Kabemoto ,  Naohiro Shibata ,  Toshiyuki Muta ,  Takayuki Shimamura ,  Hirohide Sugahara ,  Junji Nishioka ,  Takatsugu Sasaki ,  Satoshi Shinohara ,  Yozo Nakayama ,  Jun Sakurai ,  Hiroaki Ishihata ,  Takeshi Horie ,  Toshiyuki Shimizu

发明人： Akira Kabemoto ,  Naohiro Shibata ,  Toshiyuki Muta ,  Takayuki Shimamura ,  Hirohide Sugahara ,  Junji Nishioka ,  Takatsugu Sasaki ,  Satoshi Shinohara ,  Yozo Nakayama ,  Jun Sakurai ,  Hiroaki Ishihata ,  Takeshi Horie ,  Toshiyuki Shimizu

IPC分类号： G06F12/08 ,  G06F15/17 ,  G06F13/00

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F2212/2542

摘要： A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

摘要翻译： 多个处理器，每个处理器具有为多个处理器模块提供的高速缓存和其中分配和布置主存储器的本地存储器通过内部监听总线相互连接。 处理器模块通过第二系统总线相互连接。 通过使用两个单独的总线，处理器组内的高速缓存一致性操作与处理器组之外的高速缓存一致性操作保持分开。

公开(公告)号：US06546501B1

公开(公告)日：2003-04-08

申请号：US09531014

申请日：2000-03-20

申请人： Makoto Hataida ,  Manabu Nakao ,  Toshiyuki Muta

发明人： Makoto Hataida ,  Manabu Nakao ,  Toshiyuki Muta

IPC分类号： G06F1100

CPC分类号： G06F11/1064

摘要： A cache memory apparatus includes a primary cache memory using a 4-way set associative method and a secondary cache memory. When a parity error occurs in an entry in the primary cache memory, the way is prohibited from being replaced, and data related to the entry is written back from the primary cache memory to the secondary cache memory. Thereafter, the entry in the primary cache memory is made invalid, and the prohibition on the replacement of the way is released. When the secondary cache memory is accessed, the data written back is moved from the secondary cache memory to the entry into the primary cache memory to set a status before the parity error occurs.

摘要翻译： 高速缓冲存储器装置包括使用4路组关联方法和次级高速缓冲存储器的主高速缓冲存储器。 当主缓冲存储器中的条目发生奇偶校验错误时，禁止替换该方法，并将与该条目相关的数据从主缓存存储器写回到次级高速缓冲存储器。 此后，使一级高速缓冲存储器中的条目成为无效，并且释放对该方式的更换的禁止。 当二次缓存存储器被访问时，回写的数据从次级高速缓冲存储器移动到主高速缓冲存储器的条目，以在发生奇偶校验错误之前设置状态。