- 专利标题: Integrated circuitry and semiconductor processing method of forming field effect transistors
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申请号: US386076申请日: 1999-08-30
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公开(公告)号: US6093661A公开(公告)日: 2000-07-25
- 发明人: Jigish D. Trivedi , Zhongze Wang , Rongsheng Yang
- 申请人: Jigish D. Trivedi , Zhongze Wang , Rongsheng Yang
- 申请人地址: ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: ID Boise
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234 ; H01L21/31 ; H01L21/336
摘要:
In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms. Transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.
公开/授权文献
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