公开(公告)号：US06744102B2

公开(公告)日：2004-06-01

申请号：US10087416

申请日：2002-02-27

申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

IPC分类号： H01L2994

CPC分类号： H01L21/823462

摘要： In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms. Transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.

摘要翻译： 根据本发明的一个方面，形成场效应晶体管的半导体处理方法包括在被配置用于形成p型场效应晶体管的第一区域上形成第一栅极电介质层，以及第二区域，用于形成n型场效应 晶体管，半导体衬底上的两个区域。 第一栅极电介质层是在第一栅极介电层内的氮浓度为0.1％摩尔至10.0％摩尔浓度的二氧化硅，与另一个高度位置相比，在一个高度位置处的第一栅极介电层内的氮原子的浓度较高 。 第一栅介质层在第二区域上被移除，同时在第一区域上留下第一栅极介质层，并且在第二区域上形成第二栅极电介质层。 第二栅极电介质层是基本上不含氮原子的二氧化硅材料。 在第一和第二栅极电介质层上形成晶体管栅极，然后在第一区域中的晶体管栅极附近形成p型源极/漏极区域，并且在第二区域中的晶体管栅极附近形成n型源极/漏极区域 。

公开(公告)号：US06541395B1

公开(公告)日：2003-04-01

申请号：US09616959

申请日：2000-07-13

申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

IPC分类号： H01L2131

CPC分类号： H01L21/823462

摘要： In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms. Transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.

摘要翻译： 根据本发明的一个方面，形成场效应晶体管的半导体处理方法包括在被配置用于形成p型场效应晶体管的第一区域上形成第一栅极电介质层，以及第二区域，用于形成n型场效应 晶体管，半导体衬底上的两个区域。 第一栅极电介质层是在第一栅极介电层内的氮浓度为0.1％摩尔至10.0％摩尔浓度的二氧化硅，与另一个高度位置相比，在一个高度位置处的第一栅极介电层内的氮原子的浓度较高 。 第一栅介质层在第二区域上被移除，同时在第一区域上留下第一栅极介质层，并且在第二区域上形成第二栅极电介质层。 第二栅极电介质层是基本上不含氮原子的二氧化硅材料。 在第一和第二栅极电介质层上形成晶体管栅极，然后在第一区域中的晶体管栅极附近形成p型源极/漏极区域，并且在第二区域中的晶体管栅极附近形成n型源极/漏极区域 。

公开(公告)号：US06417546B2

公开(公告)日：2002-07-09

申请号：US09444024

申请日：1999-11-19

申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

IPC分类号： H01L2994

CPC分类号： H01L21/823462

摘要： In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms. Transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.

摘要翻译： 根据本发明的一个方面，形成场效应晶体管的半导体处理方法包括在被配置用于形成p型场效应晶体管的第一区域上形成第一栅极电介质层，以及第二区域，用于形成n型场效应 晶体管，半导体衬底上的两个区域。 第一栅极电介质层是在第一栅极介电层内的氮浓度为0.1％摩尔至10.0％摩尔浓度的二氧化硅，与另一个高度位置相比，在一个高度位置处的第一栅极介电层内的氮原子的浓度较高 。 第一栅介质层在第二区域上被移除，同时在第一区域上留下第一栅极介质层，并且在第二区域上形成第二栅极电介质层。 第二栅极电介质层是基本上不含氮原子的二氧化硅材料。 在第一和第二栅极电介质层上形成晶体管栅极，然后在第一区域中的晶体管栅极附近形成p型源极/漏极区域，并且在第二区域中的晶体管栅极附近形成n型源极/漏极区域 。

公开(公告)号：US6093661A

公开(公告)日：2000-07-25

申请号：US386076

申请日：1999-08-30

申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

IPC分类号： H01L21/8234 ,  H01L21/31 ,  H01L21/336

CPC分类号： H01L21/823462

摘要： In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms. Transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.

公开(公告)号：US06503805B2

公开(公告)日：2003-01-07

申请号：US09741776

申请日：2000-12-19

申请人： Zhongze Wang ,  Rongsheng Yang

发明人： Zhongze Wang ,  Rongsheng Yang

IPC分类号： H01L21336

CPC分类号： H01L29/66537 ,  H01L21/2652 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/66575

摘要： A field effect transistor having a doped region in the substrate immediately underneath the gate of the transistor and interposed between the source and drain of the transistor is provided. The doped region has a retrograde dopant profile such that the doping concentration immediately adjacent the gate is selected to allow for the formation of a channel when a threshold voltage is applied to the gate thereby eliminating the need for an enhancement doping step during formation of the transistor. The retrograde doping profile increases with the depth into the substrate which inhibits stray currents from traveling between the source and drain of the transistor in the absence of the formation of a channel as a result of voltage being applied to the gate of the transistor.

摘要翻译： 提供了在晶体管的栅极正下方具有位于晶体管的源极和漏极之间的衬底中的掺杂区域的场效应晶体管。 掺杂区域具有逆向掺杂剂分布，使得紧邻栅极的掺杂浓度被选择为允许在阈值电压施加到栅极时形成沟道，从而在形成晶体管期间不需要增强掺杂步骤 。 逆向掺杂分布随着衬底的深度而增加，其在由于施加到晶体管的栅极的电压的结果而没有形成沟道的情况下，抑制杂散电流在晶体管的源极和漏极之间传播。

公开(公告)号：US6162693A

公开(公告)日：2000-12-19

申请号：US389295

申请日：1999-09-02

申请人： Zhongze Wang ,  Rongsheng Yang

发明人： Zhongze Wang ,  Rongsheng Yang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10

CPC分类号： H01L29/66537 ,  H01L21/2652 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/66575

摘要： A field effect transistor having a doped region in the substrate immediately underneath the gate of the transistor and interposed between the source and drain of the transistor is provided. The doped region has a retrograde dopant profile such that the doping concentration immediately adjacent the gate is selected to allow for the formation of a channel when a threshold voltage is applied to the gate thereby eliminating the need for an enhancement doping step during formation of the transistor. The retrograde doping profile increases with the depth into the substrate which inhibits stray currents from traveling between the source and drain of the transistor in the absence of the formation of a channel as a result of voltage being applied to the gate of the transistor.

公开(公告)号：US20110085067A1

公开(公告)日：2011-04-14

申请号：US12967759

申请日：2010-12-14

申请人： Vincent Venezia ,  Ashish Shah ,  Rongsheng Yang ,  Duli Mao ,  Yin Qian ,  Hsin-Chih Tai ,  Howard E. Rhodes

发明人： Vincent Venezia ,  Ashish Shah ,  Rongsheng Yang ,  Duli Mao ,  Yin Qian ,  Hsin-Chih Tai ,  Howard E. Rhodes

IPC分类号： H04N5/335

CPC分类号： H01L27/1463 ,  H01L27/14601

摘要： An image sensor pixel includes a substrate, a first epitaxial layer, a collector layer, a second epitaxial layer and a light collection region. The substrate is doped to have a first conductivity type. The first epitaxial layer is disposed over the substrate and doped to have the first conductivity type as well. The collector layer is selectively disposed over at least a portion of the first epitaxial layer and doped to have a second conductivity type. The second epitaxial layer is disposed over the collector layer and doped to have the first conductivity type. The light collection region collects photo-generated charge carriers and is disposed within the second epitaxial layer. The light collection region is also doped to have the second conductivity type.

摘要翻译： 图像传感器像素包括基板，第一外延层，集电极层，第二外延层和光收集区域。 衬底被掺杂以具有第一导电类型。 第一外延层设置在衬底上并掺杂以具有第一导电类型。 集电极层选择性地设置在第一外延层的至少一部分上并被掺杂以具有第二导电类型。 第二外延层设置在集电极层上并掺杂以具有第一导电类型。 光收集区域收集光生电荷载流子并且设置在第二外延层内。 光收集区域也被掺杂以具有第二导电类型。

公开(公告)号：US20060046381A1

公开(公告)日：2006-03-02

申请号：US10925736

申请日：2004-08-24

申请人： Hongmei Wang ,  Kurt Beigel ,  Fred Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt Beigel ,  Fred Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US20120280109A1

公开(公告)日：2012-11-08

申请号：US13101991

申请日：2011-05-05

申请人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Keh-Chiang Ku ,  Rongsheng Yang

发明人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Keh-Chiang Ku ,  Rongsheng Yang

IPC分类号： H01L27/146 ,  H01L31/18

CPC分类号： H01L27/1463 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689

摘要： Techniques for promoting conductivity in a substrate for a pixel array. In an embodiment, an isolation region and a dopant well are disposed within an epitaxial layer adjoining the substrate, where a portion of the dopant well is between the substrate and a portion of the isolation well. In another embodiment, a contact is further disposed within the epitaxial layer, where a portion of the isolation region surrounds a portion of the contact.

摘要翻译： 用于促进像素阵列的衬底中的导电性的技术。 在一个实施例中，隔离区和掺杂剂阱设置在与衬底相邻的外延层内，其中掺杂剂阱的一部分位于衬底和隔离阱的一部分之间。 在另一个实施例中，接触件进一步设置在外延层内，其中隔离区域的一部分围绕接触部分。

公开(公告)号：US07875918B2

公开(公告)日：2011-01-25

申请号：US12430006

申请日：2009-04-24

申请人： Vincent Venezia ,  Ashish Shah ,  Rongsheng Yang ,  Duli Mao ,  Yin Qian ,  Hsin-Chih Tai ,  Howard E. Rhodes

发明人： Vincent Venezia ,  Ashish Shah ,  Rongsheng Yang ,  Duli Mao ,  Yin Qian ,  Hsin-Chih Tai ,  Howard E. Rhodes

IPC分类号： H01L31/062

CPC分类号： H01L27/1463 ,  H01L27/14601

摘要： An image sensor pixel includes a substrate, a first epitaxial layer, a collector layer, a second epitaxial layer and a light collection region. The substrate is doped to have a first conductivity type. The first epitaxial layer is disposed over the substrate and doped to have the first conductivity type as well. The collector layer is selectively disposed over at least a portion of the first epitaxial layer and doped to have a second conductivity type. The second epitaxial layer is disposed over the collector layer and doped to have the first conductivity type. The light collection region collects photo-generated charge carriers and is disposed within the second epitaxial layer. The light collection region is also doped to have the second conductivity type.

摘要翻译： 图像传感器像素包括基板，第一外延层，集电极层，第二外延层和光收集区域。 衬底被掺杂以具有第一导电类型。 第一外延层设置在衬底上并掺杂以具有第一导电类型。 集电极层选择性地设置在第一外延层的至少一部分上并被掺杂以具有第二导电类型。 第二外延层设置在集电极层上并掺杂以具有第一导电类型。 光收集区域收集光生电荷载流子并且设置在第二外延层内。 光收集区域也被掺杂以具有第二导电类型。