发明授权
- 专利标题: Circuit board features with reduced parasitic capacitance and method therefor
- 专利标题(中): 电路板具有降低的寄生电容及其方法
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申请号: US224011申请日: 1998-12-31
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公开(公告)号: US6103134A公开(公告)日: 2000-08-15
- 发明人: Gregory J. Dunn , Larry Lach , Jovica Savic , Allyson Beuhler , Everett Simons
- 申请人: Gregory J. Dunn , Larry Lach , Jovica Savic , Allyson Beuhler , Everett Simons
- 申请人地址: IL Schaumburg
- 专利权人: Motorola, Inc.
- 当前专利权人: Motorola, Inc.
- 当前专利权人地址: IL Schaumburg
- 主分类号: H01F17/00
- IPC分类号: H01F17/00 ; H01F41/04 ; H01L21/768 ; H01L23/522 ; H05K1/16 ; H05K3/00 ; H05K3/06 ; H05K3/46
摘要:
A method for fabricating circuit board conductors with desirable processing and reduced self and mutual capacitance. The method generally entails forming a metal layer on a positive-acting photodielectric layer formed on a substrate, and then etching the metal layer to form at least two conductor traces that cover two separate regions of the photodielectric layer while exposing a third region of the photodielectric layer between the two regions. The third region of the photodielectric layer is then irradiated and developed using the two traces as a photomask, so that the third region of the photodielectric layer is removed. The two remaining regions of the photodielectric layer masked by the traces remain on the substrate and are separated by an opening formed by the removal of the third dielectric region. As a result, the traces are not only separated by a void immediately therebetween formed when the metal layer was etched, but are also separated by the opening formed in the photodielectric layer by the removal of the third region of the photodielectric layer. Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.
公开/授权文献
- US4906550A Method of producing polydiacetylene thin film 公开/授权日:1990-03-06
信息查询
IPC分类:
H | 电学 |
H01 | 基本电气元件 |
H01F | 磁体;电感;变压器;磁性材料的选择 |
H01F17/00 | 信号类型的固定电感器 |