发明授权
US6107172A Controlled linewidth reduction during gate pattern formation using an
SiON BARC
失效
使用SiON BARC在栅极图案形成期间的受控线宽减小
- 专利标题： Controlled linewidth reduction during gate pattern formation using an SiON BARC
- 专利标题（中）： 使用SiON BARC在栅极图案形成期间的受控线宽减小
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申请号： US905104申请日： 1997-08-01
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公开(公告)号： US6107172A公开(公告)日： 2000-08-22
- 发明人: Chih-Yuh Yang , Scott A. Bell , Daniel Steckert
- 申请人： Chih-Yuh Yang , Scott A. Bell , Daniel Steckert
- 申请人地址： CA Sunnyvale
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： CA Sunnyvale
- 主分类号： H01L21/3213
- IPC分类号： H01L21/3213 ; H01L21/3205 ; H01L21/302 ; H01L21/44 ; H01L21/4763
摘要：
A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO.sub.x N.sub.y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO.sub.x N.sub.y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.
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