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    Controlled linewidth reduction during gate pattern formation using a spin-on barc
    1.
    发明授权
    Controlled linewidth reduction during gate pattern formation using a spin-on barc 失效
    使用旋转棒条在栅极图案形成期间的受控线宽减小

    公开(公告)号：US5965461A

    公开(公告)日：1999-10-12

    申请号：US905109

    申请日：1997-08-01

    申请人： Chih-Yuh Yang ,  Scott A. Bell ,  Daniel Steckert

    发明人： Chih-Yuh Yang ,  Scott A. Bell ,  Daniel Steckert

    IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/302

    CPC分类号： H01L21/28123 ,  H01L21/31138 ,  H01L21/32139 ,  Y10S438/952

    摘要： A gate is formed by depositing a gate conductive layer over a substrate layer, depositing an organic spin-on bottom anti-reflective coating (BARC) over the gate conductive layer, and forming a resist mask on the BARC. Next, the resist mask is controllably etched to further reduce the critical dimensions of gate pattern formed therein, and then the gate is formed by etching the gate conductive layer using the reduced size resist mask.

    摘要翻译： 通过在衬底层上沉积栅极导电层，在栅极导电层上沉积有机旋涂底部抗反射涂层（BARC）并在BARC上形成抗蚀剂掩模来形成栅极。 接下来，可控地蚀刻抗蚀剂掩模，以进一步减小其中形成的栅极图案的临界尺寸，然后通过使用减小尺寸的抗蚀剂掩模蚀刻栅极导电层来形成栅极。

    Controlled linewidth reduction during gate pattern formation using an SiON BARC
    2.
    发明授权
    Controlled linewidth reduction during gate pattern formation using an SiON BARC 失效
    使用SiON BARC在栅极图案形成期间的受控线宽减小

    公开(公告)号：US6107172A

    公开(公告)日：2000-08-22

    申请号：US905104

    申请日：1997-08-01

    申请人： Chih-Yuh Yang ,  Scott A. Bell ,  Daniel Steckert

    发明人： Chih-Yuh Yang ,  Scott A. Bell ,  Daniel Steckert

    IPC分类号： H01L21/3213 ,  H01L21/3205 ,  H01L21/302 ,  H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/32139 ,  Y10S438/951 ,  Y10S438/952

    摘要： A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO.sub.x N.sub.y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO.sub.x N.sub.y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.

    摘要翻译： 通过产生晶片堆叠形成栅极，该晶片堆叠包括在衬底层上的栅极导电层，在导电层上方沉积SiOxNy层以充当底部抗反射涂层（BARC），并在SiO x N y上形成抗蚀剂掩模 层。 接下来，抗蚀剂掩模被各向同性地蚀刻以进一步减小在其中形成的栅极图案的临界尺寸，然后蚀刻下面的BARC和晶片叠层以在导电层外形成栅极。

    Method for fabricating a polysilicon structure with reduced length that is beyond photolithography limitations
    3.
    发明授权
    Method for fabricating a polysilicon structure with reduced length that is beyond photolithography limitations 失效
    用于制造超过光刻限制的具有减小的长度的多晶硅结构的方法

    公开(公告)号：US6060377A

    公开(公告)日：2000-05-09

    申请号：US306874

    申请日：1999-05-07

    申请人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

    发明人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

    IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/3205

    CPC分类号： H01L21/32139 ,  H01L21/0338 ,  H01L21/28123 ,  H01L29/6659

    摘要： A polysilicon structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a masking polysilicon structure having a first predetermined length defined by sidewalls on ends of the first predetermined length of the masking polysilicon structure. The present invention also includes a step of depositing a layer of metal on the sidewalls of the masking polysilicon structure. The layer of metal has a predetermined thickness. The layer of metal reacts with the masking polysilicon structure at the sidewalls of the masking polysilicon structure in a silicidation anneal to form metal silicide. The masking polysilicon structure has a second predetermined length that is reduced from the first predetermined length when the metal silicide has consumed into the sidewalls of the masking polysilicon structure after the silicidation anneal. The second predetermined length depends on the predetermined thickness of the layer of metal deposited on the sidewalls of the masking polysilicon structure. The masking polysilicon structure has the second predetermined length and is used as a mask for etching a first layer of polysilicon to form the polysilicon structure from the first layer of polysilicon. The remaining polysilicon structure after this etch has the reduced length that is substantially equal to the second predetermined length of the masking polysilicon structure. The present invention may be used to particular advantage when the polysilicon structure having the reduced length forms a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

    摘要翻译： 通过使用硅化退火来控制缩短的长度，制造出具有减小的长度的多晶硅结构，其超过通过光刻实现的结果。 通常，本发明包括形成具有由掩模多晶硅结构的第一预定长度的端部上的侧壁限定的第一预定长度的掩模多晶硅结构的步骤。 本发明还包括在掩模多晶硅结构的侧壁上沉积金属层的步骤。 金属层具有预定的厚度。 金属层在硅化退火中在掩模多晶硅结构的侧壁处与掩模多晶硅结构反应以形成金属硅化物。 掩模多晶硅结构具有第二预定长度，当在硅化退火之后金属硅化物消耗到掩模多晶硅结构的侧壁时，该第二预定长度从第一预定长度减小。 第二预定长度取决于沉积在掩模多晶硅结构的侧壁上的金属层的预定厚度。 掩模多晶硅结构具有第二预定长度，并且用作蚀刻第一多晶硅层的掩模，以从第一多晶硅层形成多晶硅结构。 在该蚀刻之后的剩余多晶硅结构具有基本上等于掩模多晶硅结构的第二预定长度的减小的长度。 当具有减小的长度的多晶硅结构形成MOSFET（金属氧化物半导体场效应晶体管）的栅电极时，本发明可以特别有利。

    Method for fabricating a metal structure with reduced length that is beyond photolithography limitations
    5.
    发明授权
    Method for fabricating a metal structure with reduced length that is beyond photolithography limitations 失效
    用于制造超过光刻限制的具有减小的长度的金属结构的方法

    公开(公告)号：US6133129A

    公开(公告)日：2000-10-17

    申请号：US306875

    申请日：1999-05-07

    申请人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

    发明人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

    IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/3205

    CPC分类号： H01L21/28123 ,  H01L21/28079 ,  H01L21/321 ,  H01L29/66575 ,  Y10S438/947

    摘要： A metal structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a base metal structure on a semiconductor substrate. The base metal structure has a first predetermined length defined by sidewalls on ends of the first predetermined length of the base metal structure. The present invention also includes the step of depositing a layer of silicon on the sidewalls of the base metal structure, and this layer of silicon has a predetermined thickness. The layer of silicon reacts with the base metal structure at the sidewalls of the base metal structure in a silicidation anneal to form metal silicide comprised of the layer of silicon that has reacted with the base metal structure at the sidewalls of the base metal structure. The base metal structure has a second predetermined length that is reduced from the first predetermined length when the layer of silicon has consumed into the sidewalls of the base metal structure after the silicidation anneal. The second predetermined length depends on the predetermined thickness of the layer of silicon deposited on the sidewalls of the base metal structure before the silicidation anneal. After the silicidation anneal, the metal silicide is then removed from the sidewalls of the base metal structure. A remaining portion of the base metal structure, after the metal silicide is removed, forms the metal structure of the present invention having the reduced length that is substantially equal to the second predetermined length. The present invention may be used to particular advantage when the metal structure having the reduced length forms a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

    摘要翻译： 通过使用硅化退火来控制缩短的长度，制造出具有减小的长度的金属结构，其超过了通过光刻可以实现的结构。 通常，本发明包括在半导体衬底上形成贱金属结构的步骤。 贱金属结构具有由基体金属结构的第一预定长度的端部上的侧壁限定的第一预定长度。 本发明还包括在基底金属结构的侧壁上沉积硅层的步骤，并且该硅层具有预定的厚度。 硅层在贱金属结构的侧壁处与基体金属结构反应，以在硅化退火中形成金属硅化物，该金属硅化物由在贱金属结构的侧壁处与基体金属结构反应的硅层组成。 贱金属结构具有第二预定长度，当硅层在硅化退火之后消耗到基体金属结构的侧壁中时，该第一预定长度从第一预定长度减小。 第二预定长度取决于在硅化退火之前沉积在贱金属结构的侧壁上的硅层的预定厚度。 在硅化退火之后，然后从基体金属结构的侧壁去除金属硅化物。 在金属硅化物被除去之后，母体金属结构的剩余部分形成具有基本上等于第二预定长度的减小的长度的本发明的金属结构。 当具有减小的长度的金属结构形成MOSFET（金属氧化物半导体场效应晶体管）的栅电极时，本发明可以被用于特别的优点。

    Gate etch process with extended CD trim capability
    9.
    发明授权
    Gate etch process with extended CD trim capability 有权
    门蚀刻工艺具有扩展的CD修剪能力

    公开(公告)号：US06514871B1

    公开(公告)日：2003-02-04

    申请号：US09596820

    申请日：2000-06-19

    申请人： Chih-Yuh Yang ,  Scott A. Bell

    发明人： Chih-Yuh Yang ,  Scott A. Bell

    IPC分类号： H01L21302

    CPC分类号： H01L21/31138 ,  H01L21/32139 ,  Y10S438/948

    摘要： A method is provided herein for trim etching a resist line in a plasma etch apparatus. The method provides a reduced rate of vertical direction etching of the resist, and an increased rate of horizontal direction etching of the resist, by applying a lower biasing power to the plasma etch apparatus that is conventionally used. The resulting resist has an increased height in relation to its width which adds to the structural integrity of the resist line and significantly reduces problems of discontinuity in the resist line.

    摘要翻译： 本文提供了一种用于在等离子体蚀刻装置中修整蚀刻抗蚀剂线的方法。 通过对常规使用的等离子体蚀刻装置施加较低的偏压功率，该方法提供了抗蚀剂的垂直方向蚀刻的降低率和抗蚀剂的水平方向蚀刻速率的提高。 所得到的抗蚀剂相对于其宽度具有增加的高度，这增加了抗蚀剂线的结构完整性，并且显着减少了抗蚀剂线中的不连续性的问题。

    Silicon oxime spacer for preventing over-etching during local interconnect formation
    10.
    发明授权
    Silicon oxime spacer for preventing over-etching during local interconnect formation 失效
    硅肟间隔物，用于在局部互连形成期间防止过蚀刻

    公开(公告)号：US5990524A

    公开(公告)日：1999-11-23

    申请号：US993868

    申请日：1997-12-18

    申请人： William G. En ,  Minh Van Ngo ,  Chih-Yuh Yang ,  David K. Foote ,  Scott A. Bell ,  Olov B. Karlsson ,  Christopher F. Lyons

    发明人： William G. En ,  Minh Van Ngo ,  Chih-Yuh Yang ,  David K. Foote ,  Scott A. Bell ,  Olov B. Karlsson ,  Christopher F. Lyons

    IPC分类号： H01L21/768 ,  H01L29/78

    CPC分类号： H01L21/76897 ,  H01L21/76895

    摘要： During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. Improved, multipurpose spacers are provided to reduce the chances of over-etching. The multipurpose spacers are made of silicon oxime. The etching plasmas that are used to etch one or more overlying dielectric layers tend to have a higher selectivity ratio to the multipurpose spacers than to the conventional oxide spacers. Additionally, the multipurpose spacers do not tend to degrade the hot carrier injection (HCI) properties as would a typical nitride spacer.

    摘要翻译： 在半导体晶片中局部互连的镶嵌形成期间，由于将与晶体管栅极相邻的氧化物间隔物暴露于用于蚀刻一个或多个蚀刻等离子体的一个或多个蚀刻等离子体，可以将穿透区域形成为衬底， 更重叠的电介质层。 穿通区域可能会损坏晶体管电路。 提供改进的多用途间隔件以减少过度蚀刻的机会。 多用途间隔件由硅肟制成。 用于蚀刻一个或多个上覆电介质层的蚀刻等离子体与常规氧化物间隔物相比往往具有比多用途间隔物更高的选择比。 此外，多用途间隔物不会像典型的氮化物间隔物一样降低热载流子注入（HCl）性质。