The present invention relates to a structure of processor having a plurality of main processors and sub processors, and a method for sharing the sub processors, wherein a method is used for preserving a state of a register file by using a shadow register file when main processor inputs an instruction of the sub processor in case that an exceptional situation happens under processing of an instruction of sub processor and for rolling back thereafter the preserved state in case there is an information of occurrence of the exceptional situation from the sub processor. Also, in order to solve a problem that cache efficiency is reduced due to the use of a first cache which is relatively small and frequently used, there is suggested a first cache bypassing function. Further, in order to solve a problem that its processing speed is reduced when the main processor transfers instructions in sub processor, it is possible to improve the processors' parallelism and its efficiency by providing an extra register file.