A decoder comprises a first line placed at a first reference potential (V.sub.CC); a second line placed at a second reference potential switchable between the first reference potential and at least one programming potential higher than the first reference potential; a voltage elevator circuit connected to the second line, receiving a control signal and generating at an output a third reference potential switchable, on the basis of the control signal, between the first reference potential, the programming potential and a boosted potential which is between the first reference potential and the reference potential; a third line connected to the output of the voltage elevator circuit; an input circuit connected to the first line and receiving a predecoding signal, an output biasing circuit connected to said third line and generating a biasing signal for one line of the memory device; and switch circuit located between the input circuit and the biasing circuit, receiving a driving signal for selectively breaking the electrical connection between the input circuit and the biasing circuit on the basis of the driving signal.