An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.