公开(公告)号：US5819105A

公开(公告)日：1998-10-06

申请号：US566556

申请日：1995-12-04

申请人： Michael P. Moriarty ,  Michael J. Collins ,  John E. Larson ,  Gary W. Thome

发明人： Michael P. Moriarty ,  Michael J. Collins ,  John E. Larson ,  Gary W. Thome

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/00

CPC分类号： G06F12/0831 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1694

摘要： A memory controller provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When a PCI device executes a memory read, the processor cache and L2 cache are snooped in parallel with the memory read operation. Data is not provided until the snoop operation is complete. If the snoop operation indicates a modified location, a writeback operation is performed before data is provided to the PCI bus. If data is coherent between the memory and caches, data is provided from the memory to the PCI bus.

摘要翻译： 存储器控制器在处理器和PCI总线与存储器系统之间提供一系列的队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作PCI到存储器队列。 当PCI设备执行存储器读取时，处理器缓存和L2高速缓存与存储器读取操作并行地窥探。 在窥探操作完成之前，不提供数据。 如果窥探操作指示修改的位置，则在向PCI总线提供数据之前执行写回操作。 如果数据在存储器和高速缓存之间是一致的，则从存储器向PCI总线提供数据。

公开(公告)号：US5692154A

公开(公告)日：1997-11-25

申请号：US645921

申请日：1996-05-14

申请人： Brian B. Tucker ,  Gary W. Thome

发明人： Brian B. Tucker ,  Gary W. Thome

IPC分类号： G06F12/08 ,  G06F11/20 ,  G06F12/00

CPC分类号： G06F12/0888 ,  G06F12/0804 ,  G06F12/0831

摘要： Circuitry which corrects a problem in the 82424TX Cache and Dram Controller (CDC) from Intel with the addition of only minor circuitry which can be used externally or internally and which allows proper operation under all conditions. Combinatorial logic is provided to block the dirty bit provided by the dirty Static Random Access Memory (SRAM) when the processor is performing a noncacheable access as indicated by the Page Cache Disable (PCD) bit. In certain cases the PCD bit is ignored and the stored dirty bit is passed without blocking: when the AHOLD signal is asserted, indicating that an address snoop operation is occurring, and when the BOFF* signal is asserted, indicating that a cache flush or writeback operation is occurring. Thus, the dirty bit provided by the dirty SRAM when the processor is performing a non-cacheable access is selectively blocked in certain instances to ensure cache coherency.

摘要翻译： 电路可以纠正英特尔82424TX Cache和Dram控制器（CDC）中的一个问题，增加了只能在外部或内部使用的次要电路，并允许在所有条件下正常运行。 当处理器执行不可访问访问（如页缓存禁用（PCD）位）时，提供组合逻辑来阻止脏静态随机存取存储器（SRAM）提供的脏位。 在某些情况下，PCD位被忽略，并且存储的脏位不通过阻塞传递：当AHOLD信号被置位时，指示发生地址侦听操作，并且当BOFF *信号被置位时，指示缓存刷新或写回 操作正在发生。 因此，当处理器执行不可缓存访问时，由脏SRAM提供的脏位在某些情况下被选择性地阻止以确保高速缓存一致性。

公开(公告)号：US5634112A

公开(公告)日：1997-05-27

申请号：US324112

申请日：1994-10-14

申请人： Gary W. Thome ,  Michael P. Moriarty ,  John E. Larson

发明人： Gary W. Thome ,  Michael P. Moriarty ,  John E. Larson

IPC分类号： G06F13/16 ,  G06F12/06

CPC分类号： G06F13/1631

摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.

摘要翻译： 存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作PCI到存储器队列。 当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。 如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。 为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。 存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。 存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。 存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规DRAM周期的特定部分的时钟周期数。

公开(公告)号：US5596741A

公开(公告)日：1997-01-21

申请号：US538742

申请日：1995-10-03

申请人： Gary W. Thome

发明人： Gary W. Thome

IPC分类号： G06F9/38 ,  G06F1/32 ,  G06F12/14 ,  G06F13/16

CPC分类号： G06F13/1615 ,  G06F12/1491

摘要： A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices at their desired optimal speeds. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller operates in system management mode to override any write protect status of memory so that the SMRAM can be located in the main memory space and be write protected during normal operations but be full usable during system management mode.

摘要翻译： 一个内存控制器，最大程度地利用任何处理器流水线并同时运行大量的周期。 存储器控制器可以以其期望的最佳速度利用不同的速度存储器件。 这些功能由多个简单的相互依赖的状态机执行，每个状态机负责整个操作的一小部分。 当每个状态机达到完成其功能时，它通知相关状态机现在可以继续，并继续等待下一个启动或继续指示。 下一台状态机以类似的方式运行。 负责循环早期部分的状态机在下一个循环中开始执行任务，然后负责循环后期部分的状态机完成任务。 存储器控制器在逻辑上组织为三个主要块，前端块，存储器块和主机块，每个都负责与其相关总线和组件的交互，并与各种其他块进行交互。 存储器控制器以系统管理模式操作以覆盖存储器的任何写保护状态，使得SMRAM可以位于主存储器空间中，并且在正常操作期间被写保护，但是在系统管理模式期间可以完全可用。

公开(公告)号：US5509138A

公开(公告)日：1996-04-16

申请号：US34105

申请日：1993-03-22

申请人： Christine G. Cash ,  Gary W. Thome

发明人： Christine G. Cash ,  Gary W. Thome

IPC分类号： G06F12/06 ,  G06F13/16 ,  G06F12/02

CPC分类号： G06F12/0653 ,  G06F12/0684 ,  G06F13/1689

摘要： A microcomputer system with a data destination facility provides for accessing dynamic RAMs of different speeds faster or slower depending on the dynamic RAM speed. When the data destination facility maps the dynamic rams, it also saves a bit indicating whether the block of RAM is a high or low speed RAM. When the memory controller attempts to access a certain location, the data destination facility then returns the value of the speed bit associated with that block of memory to the memory controller state machine, which then omits or adds clock cycles to the memory access depending upon the speed of the memory. Further, in setting up the data destination facility, the system initialization routine determines SIMM sizes by first touching the memory locations at which the SIMMs are occupied to determine if there is memory there, and then determines the SIMM speeds based on a combination of the SIMM sizes and the SIMM identification codes returned through a standard serial shift register.

摘要翻译： 具有数据目的地设施的微计算机系统提供了根据动态RAM速度更快或更慢访问不同速度的动态RAM。 当数据目的地设施映射动态公司时，它还保存一个位，指示RAM的块是高速还是低速RAM。 当存储器控制器尝试访问特定位置时，数据目的地设备然后将与该存储器块相关联的速度位的值返回到存储器控制器状态机，然后将存储器控制器状态机省略或添加时钟周期到存储器访问，这取决于 记忆速度 此外，在建立数据目的地设施时，系统初始化例程通过首先触摸SIMM被占用的存储器位置来确定SIMM尺寸，以确定是否存在存储器，然后基于SIMM的组合来确定SIMM速度 尺寸和通过标准串行移位寄存器返回的SIMM识别码。

公开(公告)号：US06215504B1

公开(公告)日：2001-04-10

申请号：US08905685

申请日：1997-08-01

申请人： Brian E. Longhenry ,  Gary W. Thome ,  John S. Thayer

发明人： Brian E. Longhenry ,  Gary W. Thome ,  John S. Thayer

IPC分类号： G06T1120

CPC分类号： G06T3/40

摘要： A routable operand and selectable operation processor multimedia extension unit is employed to draw lines in a video system using an efficient, parallel technique. A first series of integral y pixel values and error values are calculated according to Bresenham's line drawing algorithm. Then, subsequent pixels and error values are calculated in parallel based on the previously calculated values.

摘要翻译： 使用可路由操作数和可选择的操作处理器多媒体扩展单元来使用有效的并行技术在视频系统中绘制线。 根据Bresenham的线图算法计算第一系列积分y像素值和误差值。 然后，基于先前计算的值并行计算后续像素和误差值。

公开(公告)号：US6154831A

公开(公告)日：2000-11-28

申请号：US296356

申请日：1999-04-22

申请人： John S. Thayer ,  Gary W. Thome ,  John G. Favor ,  Frederick D. Weber

发明人： John S. Thayer ,  Gary W. Thome ,  John G. Favor ,  Frederick D. Weber

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38 ,  G06F9/34

CPC分类号： G06F9/3885 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3824

摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The MEU may include a plurality of ALUs, registers partitioned into slots, and a decode unit for decoding an instruction specifying operands from any slot from one register and from a fixed slot of another register as well as different operations to be performed by the ALUs on the operands.

摘要翻译： 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 MEU可以包括多个ALU，被划分成时隙的寄存器，以及解码单元，用于对来自一个寄存器和另一个寄存器的固定时隙的任何时隙指定操作数的指令进行解码，以及由ALU执行的不同操作 操作数。

公开(公告)号：US6115791A

公开(公告)日：2000-09-05

申请号：US48577

申请日：1998-03-26

申请人： Michael J. Collins ,  Gary W. Thome

发明人： Michael J. Collins ,  Gary W. Thome

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F12/0897

摘要： An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.

摘要翻译： 一种用于在解码特殊冲洗确认周期时监视和解码处理器总线周期并刷新第二级高速缓存的装置。 CPU优选地包括内部高速缓存和用于接收命令CPU冲洗其内部高速缓存的信号的刷新输入。 通过执行任何必要的循环来刷新脏数据到主存储器后，CPU执行特殊的刷新确认周期，以通知外部设备冲洗过程已经完成。 缓存控制器检测刷新确认周期，并向第二级缓存提供刷新信号。 然后，缓存控制器向CPU提供周期信号的结束以指示冲洗周期已被确认。

公开(公告)号：US5892964A

公开(公告)日：1999-04-06

申请号：US885062

申请日：1997-06-30

申请人： Ronald Timothy Horan ,  Gary W. Thome ,  Sompong Olarig

发明人： Ronald Timothy Horan ,  Gary W. Thome ,  Sompong Olarig

IPC分类号： G06F13/38 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027 ,  G06F13/385

摘要： A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port ("AGP") bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect ("PCI") device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request ("REQ") and Grant ("GNT") signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.

公开(公告)号：US5857116A

公开(公告)日：1999-01-05

申请号：US918838

申请日：1997-08-26

申请人： Basem Abu Ayash ,  Gary W. Thome

发明人： Basem Abu Ayash ,  Gary W. Thome

IPC分类号： G06F12/02

CPC分类号： G06F12/02

摘要： A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

摘要翻译： 当计算机处于系统管理模式时，用于计算机的系统管理模式地址校正系统在地址总线上提供正确的地址值。 通常，微处理器地址输出的位20可以通过声明FORCE A20信号来屏蔽。 计算机系统还以系统管理模式操作，这要求所有地址位可用于正确访问系统管理中断向量。 当计算机处于系统管理模式时，计算机的微处理器断言系统管理中断激活（SMIACT *）信号。 该信号被提供给也接收FORCE A20信号的电路。 当SMIACT信号被禁用时，控制电路将真实的FORCE A20信号提供给计算机系统。 发生SMI时，SMIACT信号被激活，并且FORCE A20信号被禁止。 结果，微处理器产生的地址在地址总线上被断言。