发明授权
US6118693A Electrically erasable non-volatile memory cell with integrated SRAM cell
to reduce testing time
失效
具有集成SRAM单元的电可擦除非易失性存储单元，以减少测试时间
- 专利标题： Electrically erasable non-volatile memory cell with integrated SRAM cell to reduce testing time
- 专利标题（中）： 具有集成SRAM单元的电可擦除非易失性存储单元，以减少测试时间
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申请号： US320389申请日： 1999-05-26
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公开(公告)号： US6118693A公开(公告)日： 2000-09-12
- 发明人: Benny Ma
- 申请人： Benny Ma
- 申请人地址： OR Hillsboro
- 专利权人： Lattice Semiconductor Corporation
- 当前专利权人： Lattice Semiconductor Corporation
- 当前专利权人地址： OR Hillsboro
- 主分类号： G11C11/00
- IPC分类号： G11C11/00 ; G11C29/24 ; G11C16/04
摘要：
In a programmable integrated circuit, by providing a static random access memory (SRAM) cell in each electrically erasable (E.sup.2) non-volatile memory cell, testing time of circuits configured by the E.sup.2 non-volatile memory cells can be reduced substantially. In one embodiment, the SRAM cell can be included by providing a small number of transistors to recirculate the output value of an inverting buffer. During testing, a logic value is written into the SRAM cell in place of the logic value in the non-volatile storage of the E.sup.2 non-volatile memory cell. In one embodiment, the E.sup.2 non-volatile memory cell can be used in conjunction with a 1-bit shift-register. Multiple 1-bit shift registers can be used as a scan chain to scan into the SRAM cells of multiple E.sup.2 non-volatile memory cells.
公开/授权文献
- USD322206S Portable power saw 公开/授权日：1991-12-10
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