发明授权
US6128356A CMOS circuit composed of CMOS circuit blocks arranged in bit-parallel
data paths
失效
CMOS电路由排列在位并行数据路径中的CMOS电路块组成
- 专利标题： CMOS circuit composed of CMOS circuit blocks arranged in bit-parallel data paths
- 专利标题（中）： CMOS电路由排列在位并行数据路径中的CMOS电路块组成
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申请号： US890306申请日： 1997-07-09
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公开(公告)号： US6128356A公开(公告)日： 2000-10-03
- 发明人: Ulrich Kleine , Mike Vogel
- 申请人： Ulrich Kleine , Mike Vogel
- 申请人地址： DEX Munich
- 专利权人： Siemens Aktiengesellschaft
- 当前专利权人： Siemens Aktiengesellschaft
- 当前专利权人地址： DEX Munich
- 优先权： DEX19627634 19960709
- 主分类号： G06F13/42
- IPC分类号： G06F13/42 ; G11C19/38 ; H03K19/0175 ; H04L7/00
摘要：
Data transmission through data paths is synchronized using a symmetrical clock signal. In order to avoid dynamic hazards, which arise due to different delay times during data transmission in the data paths, an intermediate storage element is respectively arranged in each data path. It does not forward the received data signals into the subsequent circuit blocks until towards the end of the clock signal impulse used for the synchronization of the data transmission.