A distributed clocking mechanism is provided for synchronous digital designs. Each functional unit in the design is associated with a distributed clock unit that generates controlled local clocks. The clock period and the pulse width of local clock can be varied. Multiple clocks with varying phases are generated. The local clocks are synchronized with other local clocks and also with external clock. This controlled, distributed clocking mechanism provides flexibility to the design, increases performance, and reduces power consumption and noise of the device in comparison to traditional synchronous central clocking mechanism. This mechanism also enables the design to operate with multiple external clocks allowing for easy integration of multiple functionality to the design.