公开(公告)号：US6065126A

公开(公告)日：2000-05-16

申请号：US17278

申请日：1998-02-02

申请人： Thang Minh Tran ,  Rupaka Mahalingaiah

发明人： Thang Minh Tran ,  Rupaka Mahalingaiah

IPC分类号： G06F1/10 ,  G06F9/38 ,  G06F1/12

CPC分类号： G06F9/3804 ,  G06F1/10

摘要： A self-timed and self-enabled distributed clock is provided for a functional unit that has variable executing time. The self-timed clock provides plurality of clock pulses within a clock cycle for latching of result and starting execution of the next operation. The functional unit can execute more than one operation per clock cycle thus increasing the utilization of the execute unit and the performance of the processor. The state machine is designed to keep track of the current clock pulse and the execution time of the current operation. The functional unit includes the output queue buffer to keep plurality of results from execute unit. The functional unit executes data close to its optimal timing while the data between functional units are synchronized on the clock boundary as in synchronous design. It is more efficient than synchronous design yet the outputs are deterministic as the clocking is preserved in the design.

摘要翻译： 为具有可变执行时间的功能单元提供自定时和自启动分布式时钟。 自定时钟在时钟周期内提供多个时钟脉冲，用于锁存结果并开始执行下一个操作。 功能单元可以在每个时钟周期执行多个操作，从而增加了执行单元的使用和处理器的性能。 状态机设计用于跟踪当前时钟脉冲和当前操作的执行时间。 功能单元包括输出队列缓冲器，以保持来自执行单元的多个结果。 在同步设计中，功能单元在时钟边界上同步功能单元之间的数据，执行接近其最佳定时的数据。 它比同步设计更有效率，但输出是确定性的，因为设计中保留了时钟。

公开(公告)号：US6134670A

公开(公告)日：2000-10-17

申请号：US17418

申请日：1998-02-02

申请人： Rupaka Mahalingaiah

发明人： Rupaka Mahalingaiah

IPC分类号： G06F1/10 ,  G06F1/12

CPC分类号： G06F1/10

摘要： A distributed clocking mechanism is provided for synchronous digital designs. Each functional unit in the design is associated with a distributed clock unit that generates controlled local clocks. The clock period and the pulse width of local clock can be varied. Multiple clocks with varying phases are generated. The local clocks are synchronized with other local clocks and also with external clock. This controlled, distributed clocking mechanism provides flexibility to the design, increases performance, and reduces power consumption and noise of the device in comparison to traditional synchronous central clocking mechanism. This mechanism also enables the design to operate with multiple external clocks allowing for easy integration of multiple functionality to the design.

摘要翻译： 为同步数字设计提供分布式时钟机制。 设计中的每个功能单元与生成受控本地时钟的分布式时钟单元相关联。 时钟周期和本地时钟的脉冲宽度可以变化。 产生具有不同相位的多个时钟。 本地时钟与其他本地时钟同步，并与外部时钟同步。 与传统的同步中心计时机制相比，这种受控的分布式时钟机制提供了设计的灵活性，增加了性能，降低了设备的功耗和噪声。 该机制还使设计能够与多个外部时钟一起工作，从而可以轻松地将多种功能集成到设计中。