发明授权
US6140208A Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI
applications
有权
浅沟槽隔离(STI),双层氧化物氮化物用于VLSI应用
- 专利标题: Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications
- 专利标题(中): 浅沟槽隔离(STI),双层氧化物氮化物用于VLSI应用
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申请号: US245958申请日: 1999-02-05
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公开(公告)号: US6140208A公开(公告)日: 2000-10-31
- 发明人: Farid Agahi , Gary Bronner , Bertrand Flietner , Erwin Hammerl , Herbert Ho , Radhika Srinivasan
- 申请人: Farid Agahi , Gary Bronner , Bertrand Flietner , Erwin Hammerl , Herbert Ho , Radhika Srinivasan
- 申请人地址: NY Armonk CA San Jose
- 专利权人: International Business Machines Corporation,Infineon Technologies North America Corp.
- 当前专利权人: International Business Machines Corporation,Infineon Technologies North America Corp.
- 当前专利权人地址: NY Armonk CA San Jose
- 主分类号: H01L21/76
- IPC分类号: H01L21/76 ; H01L21/762
摘要:
A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.
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