A display device disclosed includes a liquid crystal display panel, a signal-line driver circuit responsive to image data Data and a first clock signal CK1 for generating signals supplied to signal lines, a control signal generator circuit (12) responsive to a reference clock signal for generating and issuing first clock signal CK1 and adjustment clock signals SCK, and a delay-time adjuster circuit (14) which delays the image data by a specified time interval based on a corresponding adjustment clock signal SCK from the control signal generator circuit (12) to adjust the delay time of the first clock signal CK1 as generated by the control signal generator circuit (12) with respect to the image data Data, wherein this delay-time adjuster circuit (14) is provided with phase-locked loop or PLL circuits (16) for correction of the adjustment clock signals SCK, and a PLL circuit (34) for correction of the first clock signal CK1 being supplied to the signal-line driver circuit, thereby causing the first clock signal CK1 and the image data Data to be kept exactly in phase with each other.