摘要:
A flat-panel display device includes a display panel having a plurality of pixels arrayed in a matrix, the pixels in each row forming one horizontal pixel array, first to eighth driver sections arranged in series to divide pixels in each horizontal pixel array into eight pixel blocks, for driving the pixel blocks, respectively, first and second data supply buses each connected to at least one of the driver sections, and a liquid crystal controller for distributing pixel data sequentially supplied from outside to the first and second data supply buses. In particular, the liquid crystal controller includes a data distributing circuit having a plurality of memories each of which stores items of pixel data for one pixel block and is capable of reading from one area while writing to another area, a total memory capacity of the memories being smaller than a memory capacity required for storing all items of pixel data for one horizontal pixel array, and a sequence controller for performing a control of dividing pixel data items sequentially supplied from outside into pixel-data blocks each consisting of the same number of pixel data items, equivalent to the number of pixels forming one pixel block, sequentially writing two pixel-data blocks in two memories, reading two pixel-data blocks stored in the two memories in parallel while writing is performed, and supplying the two pixel-data blocks to corresponding ones of the first and second data supply buses.
摘要:
A display device disclosed includes a liquid crystal display panel, a signal-line driver circuit responsive to image data Data and a first clock signal CK1 for generating signals supplied to signal lines, a control signal generator circuit (12) responsive to a reference clock signal for generating and issuing first clock signal CK1 and adjustment clock signals SCK, and a delay-time adjuster circuit (14) which delays the image data by a specified time interval based on a corresponding adjustment clock signal SCK from the control signal generator circuit (12) to adjust the delay time of the first clock signal CK1 as generated by the control signal generator circuit (12) with respect to the image data Data, wherein this delay-time adjuster circuit (14) is provided with phase-locked loop or PLL circuits (16) for correction of the adjustment clock signals SCK, and a PLL circuit (34) for correction of the first clock signal CK1 being supplied to the signal-line driver circuit, thereby causing the first clock signal CK1 and the image data Data to be kept exactly in phase with each other.
摘要:
A picture control device is used for driving a flat-panel display having a plurality of horizontal pixel lines each formed of display pixels arranged in one line, and composed of first and second driver groups which are arranged to divide the display pixels into groups and drive the groups of display pixels, respectively, and a drive circuit board for controlling the driver groups to output pixel data assigned to the respective display pixels during a scanning period for each horizontal pixel line and to drive the display pixels according to the pixel data. In particular, the drive circuit board includes a gate-array control section connected to the first and second driver groups by first and second wiring lines electrically separated from each other, for distributing pixel data assigned to the display pixels of each group to a corresponding driving group via a corresponding wiring line.